Archive for May, 2008

One Goal, Two Faces

Thursday, May 29th, 2008

“Offshore drilling?”

That’s what a puzzled ASIC designer would have asked with bewilderment if you mentioned the term “off-shoring” 10 years ago. But today the world is flat and off-shoring means global teams, working ’round the clock in 6 cities on 3 continents in 4 timezones on 1 chip. And it’s not just off-shoring and out-sourcing driving this globalization. Design teams for complex chips can have 100 - 150 designers doing tasks ranging from RTL design, verification, physical design, software and firmware development, mixed signal design, and so on. You just can’t find all the designers you need with the right expertise in one place or even in one company.

There are economic factors causing us to work remotely as well. Last week, American Airlines announced that they would start charging for baggage and other airlines are also raising their fares due to record oil prices. Companies, already watching the bottom line, are encouraging their people to travel less, just as they did several years ago after 9/11. Telecommuting has become accepted, even encouraged in many companies as a way to promote better employee lifestyles, save on office space, and be more “green”. As a result, for most of us, the days of the co-located design teams are as long gone as Hillary’s campaign.

Of course, these same ASIC and software design teams have designed and continue to design the technologies that enable effective collaboration between these dispersed teams. The high-speed networks that are the backbone that make it all possible. The IP routers. The graphics and specialized processors.

And let’s not forget the software applications that run on this hardware … Wikis for collaboration … WebEx, Sametime, and NetMeeting for remote meetings … Skype and Vonage for cheap global conferencing … video-conferencing … instant messaging … Twitter … Second Life … social networks like LinkedIn and FaceBook.

These technologies are impressive. Several years ago, I worked out of my home in Southern California, managing projects with team members in Silicon Valley, Arizona, Colorado, Washington State, Vancouver, Texas, Florida, Ottawa, and Bangalore. We conference called and held WebEx meetings. We worked on the same hosted environment through secure VPN. When necessary, we got up early (5 AM) or stayed up late (1 AM) to collaborate with team members half-way around the world. And these teams were able to get the job done as a result of their strong skills, hard work, and the technology that allowed them to work together. But, something was still missing and thanks to my sister-in-law I now realize what it was.

Face Time!

Our kids keep us pretty busy, so when Evelyn suggested that we need more “face time” with our kids, Joyce and I were flabbergasted. More face time? Don’t we already spend enough time getting them ready for school, dinner, or bed, taking them to this or that activity, helping with homework? Are there more than 24 hours in a day?

The truth is, although these parenting activities are important, they are not really face time. Face time is not about getting things done … it’s about getting to know one another better. Obviously, this makes a lot of sense if you are a parent, but you’re probably wondering what face time has to do with ASIC design? After all, this isn’t eHarmony or Parenting 101.

Several years ago, I attended a one-day class entitled Managing Virtually: What Works, taught by Lu Ellen Schafer of Global Savvy. Lu Ellen gave great advice on using email effectively, “drive-by-phoning” to stay in touch, collaboration tools, and especially on the difference between cultures (fascinating). But one thing stood out that she said. “Initial face-to-face interaction leads to greater remote communication.” She continued by pointing out that “informal email exchanges often do not happen among new team members until they meet face-to-face”. My friend Ron put it another way, “email is a great way to continue a relationship and a lousy way to start one”. And studies have shown this as well.

As for me, much of my day is consumed by discussions, meetings, and conference calls with co-workers, clients, and vendors. But that’s not really face time, even the face-2-face meetings. Face time is about getting to know one another and what the other person cares about. It’s something I’ve tried to do, but probably did not do enough. Go out to lunch. Go to a ballgame. Take a flight to meet a new person in the organization or on the team. Plan a team-building event and fly in the remote people. I’ve always found it easy to find excuses not to do these things … too busy … no budget … next time. But in the end, I always regret it because there is something missing. Something that feels like “trust”.

As a program manager, I recall three specific situations in which there was not enough trust because there was not enough face-time. In one case, there was some very nasty inter-personal conflict happening, but neither party trusted me enough to share their concerns until the situation was too far along. In another case, one remote team member felt he was being ignored by another remote team member, but he did not want to “bother” me with the issue. In the third instance, one team member decided to overrule another team member’s recommendations because “he knew better”. In that last case, once they met face-to-face, these two designers became a great tandem.

We all have to decide … Face Time or FaceBook?

This is not just a philosophical question but a practical one. I became aware a few days ago of a new social media company called Xuropa. From what I can gather from the website, the Xuropa Tradeshow Platform let’s you attend tradeshows at your desk. There are booths, suites, labs, demos … just like DAC, without the face time. So next year you may have a choice, DAC or eDAC?

As for me, I’m gonna have lunch on Friday with some people I haven’t seen in months. What about you?

harry the ASIC guy

Bloggers Flock to DAC Birds-of-a-Feather Session

Friday, May 23rd, 2008


Every year on March 19th, the swallows wing their way back to San Juan Capistrano. Just up the road in Anaheim, designers from around the world will fly in for the 45th Annual Design Automation Conference, held June 8th - 13th. How appropriate will it be then, when EDA and ASIC design bloggers flock to the 1st annual DAC Birds-of-a-Feather session on blogging?

Perhaps you are a blogger or are thinking of becoming a blogger or know somebody who is a blogger. Perhaps you are a marketing director or just curious. Whatever your interest, you’ll want to come meet and engage with the bloggers who are growing in quantity, quality and industry influence:

This event will be held in Rooms 201B and 201C at the Anaheim convention center on Wednesday, June 11 at 6pm.

I am helping to coordinate this session, so if you are planning to attend, just drop a quick email to harry {at} theASICguy {dot} com so we can get an idea for how large a group we will have. If you are a blogger and would like to present or be part of a panel, please let me know as well.

I hope to see and meet many of you there.

harry the ASIC guy

Big DAC Attack

Tuesday, May 20th, 2008

OK … I’m registered to go to DAC for at least one day, maybe two. I’ll definitely be there on Tuesday and probably Wednesday evening for a Blogging “Birds-of-a-Feather” session that JL Gray is setting up. Besides hitting the forums and other activities, I’ll have about half a day to attack the exhibit floor or the “suites” to look at some new technology. If you want to meet up, drop me an email and we can arrange something.

Cadence won’t be there and I already talk to Synopsys and Mentor on a regular basis, so I’m planning on focusing on smaller companies with new technology. Here’s what’s on my list so far…

Nusym - They have some new “Path Tracing” technology that finds correlations between a constrained random testbench and hard-to-hit functional coverage points. With this knowledge, they claim to be able to modify the constraints to guide the simulation to hit the coverage points. The main benefit is in getting that last few % of functional coverage that can be difficult with unguided constrained random patterns.

Chip Estimate - Having been around for a few years and recently bought by Cadence, they are basically a portal where you can access 3rd party IP and use the information to do a rough chip floorplan. This allows you to estimate area, power, yield, etc. I’m real curious as to their business model and why Cadence bought them. At a minimum, it should be entertaining to see the hyper-competitive IP vendors present back-to-back at half hour intervals on the DAC floor.

I have a few others on my list, but there are so many small companies that it’s hard to go thru them all and decide what to see. That’s where I need your help.

What would you recommend seeing and why?

Is IP a 4-letter Word ???

Friday, May 9th, 2008

As I’ve been thinking a lot about Intellectual Property (IP) lately, I recently recalled a consulting project that I had led several years ago … I think it was 2002. The client was designing a processor chip that had a PowerPC core and several peripherals. The core and some of the peripherals were purchased IP and our job was to help with the verification and synthesis of the chip.

Shaun was responsible for the verification. As he started to verify one of the interfaces, he started to uncover bugs in the associated peripheral, which was purchased IP. We contacted the IP provider and were told most assuredly that it had all been 100% verified and silicon proven. But we kept finding bugs. Eventually, faced with undeniable proof of the poor quality of their IP, they finally fessed up. It seems the designer responsible for verifying the design had left the company half way through the project. They never finished the verification. Ugh 1!

Meanwhile, Suzanne was helping with synthesis of the chip, including the PowerPC core. No matter what she did, she kept finding timing issues in the core. Eventually, she dug into the PowerPC core enough to figure out what was going on. Latches! They had used latches in order to meet timing. All well and good, but the timing constraints supplied with the design did not reflect any of that. Ugh 2!

About a week later, I was called to a meeting with Gus, who was the client’s project lead’s boss’s boss. As I walked into his office, he said something that I’ll never forget …

“I’m beginning to believe that IP is a 4-letter word”.

How true. Almost every IP I have every encountered, be it a complex mixed-signal hard IP block, a synthesizable processor core, an IO library … they all have issues. How can an industry survive when the majority of the products don’t work? Do you think the HDTV market would be around if more than half the TVs did not work? Or any market. Yet this is tolerated for IP.

That is not to say that some IP providers don’t take quality seriously. Synopsys learned it’s lesson many years ago when it came out with a PCI core that was a quality disaster. To their credit, they took failure as a learning opportunity, developed a robust reuse methodology along with Mentor Graphics, and reintroduced a PCI core that is still in use today.

Still … no IP is 100% perfect out-of-the-box. IP providers need to have a relationship and business model with their customers that encourages open sharing of design flaws. This is a two-way street. The IP provider must notify its customers when it finds bugs, and the customer must inform the IP provider when it finds bugs. As an example, Synopsys and many other reputable IP providers will inform customers of any design issue immediately, a transparency that I could have only prayed for from the company providing IP to my client. In return, they need their customers support by reporting design issues to them. Sounds simple, right?

Maybe not. I had another client who discovered during verification that there was a bug in a USB Host Controller IP. They had debugged and corrected the problem already, so I asked the project manager if they had informed the IP provider yet. He refused. The rationale? He wanted his competition to have the buggy design while he had the only fix!

We, as users, play a role because we have a responsibility to report bugs for the good of all of us using the product. Karen Bartleson talks about a similar situation with her luggage provider, where customers are encouraged to send back their broken luggage in order to help the company improve their luggage design. The luggage gets better and better as a result.

So, besides reporting bugs and choosing IP carefully, what else can we as designers do to drive IP quality. I have one idea. One day, when I have some free time, I’d like to start an independent organization that would objectively assess and grade IP. We’d take it though all the tools and flows and look at all the views, logical and physical, and come out with an assessment. This type of open grading system would encourage vendors to improve their IP and would allow us to make more informed choices rather than playing Russian Roulette.

I’m half inclined to start one today … anybody with me?

harry the ASIC guy

The Power of Wikipedia - 1.21 GigaWatts

Sunday, May 4th, 2008

On Wed April 30th Hewlett Packard announced that they had fabricated a device previously only theorized. Known as a memristor, this is the 4th basic type of passive circuit element, joining its brethren the resistor, capacitor, and inductor. The device’s unique property of “memristance” is equal to the rate of chance of flux with respect to charge, hence it has been commonly compared to the mythical “flux capacitor”, popularized in the original Back to The Future movie. Now, in order for us to achieve time travel, someone simply needs to invent the Mr. Fusion Home Energy Reactor to generate the 1.21 GigaWatts needed to power the memristor. Anybody …. Anybody … Anybody …

The memristor is said to be absolutely unique because it is the only one of the basic circuit elements to exhibit the property of memory. According to UC Berkeley Professor Leon Chua, who first postulated the existence of the memristor in 1971, “the memristor is our salvation, because it works better and better as you make it smaller and smaller. The era of nanoscale electronics will be enabled by the memristor. This is not just an invention, it is a basic scientific discovery. It has always been there — we just had to face these nanoscale problems to realize its importance.”

The applications being described include ultra-dense (100Gbit) non-volatile memory, ultra-high-density crossbar switches, and brain-like neural networks. One comment on a blog site this week from a John Conner even said “This is the beginning of SkyNet. Soon the T101 model will be developed, based on this design.” And many new applications will emerge once that the technology achieves production quality.

In a word, Wow!

Personally, I’m not at all familiar with the science behind this discovery, so I decided to do some research of my own. Since this was such an important discovery, where would I go? Wikipedia, of course.

By the end of the next day after the discovery was announced, the Wikipedia article for Memristor has been updated 110 separate times by 53 different authors. Here is the article before the announcement, and here is the article at the end of the next day. This is the 1.21 GigaWatt power of Wikipedia .. harnessing the efforts of scores of volunteers worldwide.

To be fair, I decided to try to search for “memristor” in the other three online encyclopedias.

  • The time honored Britannica.com returned “sorry, we were unable to find results for your search”.
  • Encyclopedia.com (aka Columbia Encyclopedia) returned a blank page except for Google Adsense ads for 3 art sites, including one for Dog Art (hmmmm)
  • Encarta returned “No results were found for your search in Encarta. Did you spell your search words correctly?”

Anybody …. Anybody … Anybody …

Like Ferris Bueller, I guess they were taking the day off.

harry the ASIC guy