Is IP a 4-letter Word ???

As I’ve been thinking a lot about Intellectual Property (IP) lately, I recently recalled a consulting project that I had led several years ago … I think it was 2002. The client was designing a processor chip that had a PowerPC core and several peripherals. The core and some of the peripherals were purchased IP and our job was to help with the verification and synthesis of the chip.

Shaun was responsible for the verification. As he started to verify one of the interfaces, he started to uncover bugs in the associated peripheral, which was purchased IP. We contacted the IP provider and were told most assuredly that it had all been 100% verified and silicon proven. But we kept finding bugs. Eventually, faced with undeniable proof of the poor quality of their IP, they finally fessed up. It seems the designer responsible for verifying the design had left the company half way through the project. They never finished the verification. Ugh 1!

Meanwhile, Suzanne was helping with synthesis of the chip, including the PowerPC core. No matter what she did, she kept finding timing issues in the core. Eventually, she dug into the PowerPC core enough to figure out what was going on. Latches! They had used latches in order to meet timing. All well and good, but the timing constraints supplied with the design did not reflect any of that. Ugh 2!

About a week later, I was called to a meeting with Gus, who was the client’s project lead’s boss’s boss. As I walked into his office, he said something that I’ll never forget …

“I’m beginning to believe that IP is a 4-letter word”.

How true. Almost every IP I have every encountered, be it a complex mixed-signal hard IP block, a synthesizable processor core, an IO library … they all have issues. How can an industry survive when the majority of the products don’t work? Do you think the HDTV market would be around if more than half the TVs did not work? Or any market. Yet this is tolerated for IP.

That is not to say that some IP providers don’t take quality seriously. Synopsys learned it’s lesson many years ago when it came out with a PCI core that was a quality disaster. To their credit, they took failure as a learning opportunity, developed a robust reuse methodology along with Mentor Graphics, and reintroduced a PCI core that is still in use today.

Still … no IP is 100% perfect out-of-the-box. IP providers need to have a relationship and business model with their customers that encourages open sharing of design flaws. This is a two-way street. The IP provider must notify its customers when it finds bugs, and the customer must inform the IP provider when it finds bugs. As an example, Synopsys and many other reputable IP providers will inform customers of any design issue immediately, a transparency that I could have only prayed for from the company providing IP to my client. In return, they need their customers support by reporting design issues to them. Sounds simple, right?

Maybe not. I had another client who discovered during verification that there was a bug in a USB Host Controller IP. They had debugged and corrected the problem already, so I asked the project manager if they had informed the IP provider yet. He refused. The rationale? He wanted his competition to have the buggy design while he had the only fix!

We, as users, play a role because we have a responsibility to report bugs for the good of all of us using the product. Karen Bartleson talks about a similar situation with her luggage provider, where customers are encouraged to send back their broken luggage in order to help the company improve their luggage design. The luggage gets better and better as a result.

So, besides reporting bugs and choosing IP carefully, what else can we as designers do to drive IP quality. I have one idea. One day, when I have some free time, I’d like to start an independent organization that would objectively assess and grade IP. We’d take it though all the tools and flows and look at all the views, logical and physical, and come out with an assessment. This type of open grading system would encourage vendors to improve their IP and would allow us to make more informed choices rather than playing Russian Roulette.

I’m half inclined to start one today … anybody with me?

harry the ASIC guy

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9 Responses to “Is IP a 4-letter Word ???”

  1. John Eaton Says:

    I am amazed that the asic design process hasn’t collapsed under it’s own weight. We have 50-100 designers around the world from a dozen different companies creating components that we stitch together into chips.

    When you do something like that with designers creating cards that will plug into a mainframe then you usually have enough sense to publish a bus spec
    to tell everybody what signals that they will need to create and what they can expect from the mainframe.

    Has anyone seen such a spec for digital components? I have seen a lot of
    guidelines but nobody has ever published them together in one place.

    We need a single document that tells designers what they can and cannot do in their designs as well as rtl checkers that will catch any deviations.

    When you get a new piece of code you need to have an incoming inspection
    tool that can expose anything strange as soon as possible.

    John Eaton

  2. Harry the ASIC guy Says:

    Thanks for your comments John.

    At DVCON this year, I think they were talking about teams of 100-150 designers doing the most complex chips, so the team size you gave seems right in that range.

    There are a only handful of bus specs that are standards and common enough to have catalyzed a significant quantity of IP. For internal busses, AHB and AXI come to mind most readily. Externally, the PCI family and USB families. In all these cases, the spec is well documented and there is some golden validation, e.g. plugfest for hardware and VIP conformance tests for RTL. If I want to buy any of these IP, at least I can know if they passed these industry standard tests.

    For other IP, there are no standard tests. The only “benchmark” for quality for these IP is the QIP metric that VSIA developed and is now managed by IEEE. But that is all self-graded and I don’t see that used much, so it’s not that helpful.

  3. JL Gray Says:

    Interesting article. Thanks Harry!

    JL

  4. Mike Mintz Says:

    Hi Harry,

    >anybody with me?

    Absolutely!!!!

    Here’s my take on what we need to do to get there. I think it’s a logical extension of your idea.

    Provide INDEPENDENT OPEN_SOURCE Verification IP. Let the cores companies charge for the IP, but let’s see if we can get them to be tested on some standard verification IP.

    Take Care,
    Mike

  5. danubi1 Says:

    How about we let users rate their experiences with the IP, in an Amazon like market place? That way potential buyers could find out what other users are saying about the IP they are thinking about purchasing, and the IP providers would be naked!

    Just a thought..

    Kwam

  6. harry Says:

    >How about we let users rate their experiences with the IP, in an
    >Amazon like market place? That way potential buyers could find
    >out what other users are saying about the IP they are thinking
    >about purchasing, and the IP providers would be naked!

    Thanks, Kwam. Now I can’t get the picture of naked IP providers out of my head :-o

    Seriously, I think this sort of transparency works under certain circumstances:

    1) There is a single portal (or a few portals). For books, there is Amazon and B&N and that’s 95% or the online market, so there is critical mass where you can go and find the reviews. A counterexample is hotel or other product reviews, where I can find many places to get these and not critical mass in one place. For IP, there are a few portals such and Design & Reuse and Chip Estimate (now Cadence) that have most IP, so its possible that this might work. (In fact, I’ve been scratching my head about why Cadence bought ChipEstimate and all I can come up with is this portal idea).

    2) The rating is independent and fair. Sites like the one mentioned above don’t want to alienate the IP providers or they will lose the advertising revenue on which they survive. Can you trust a PCIExpress rating if the IP provider is one of the advertising clients? If the site only passes on user ratings (like Amazon), then at least that bias is gone.

    3) The rating is dynamic. IP is dynamic and can improve over time, so it’s important that old ratings and reviews that don’t apply can be flushed out. This is I think the biggest difference between IP and books, which are static. Still, by tracking the dates of the reviews and ratings, one could come up with a trend line that would indicate quality over time.

    In addition to the rating, I think there needs to be specific detailed data to the IP provider on what is broken (see the baggage example). It’s not always the IP provider’s fault. The IP can work in one release of the tools and not in the next. The goal is not to punish IP providers, but to give them the tools to to make their IP better. I’d even give them our test suite so they can get it right out-of-the-gate.

  7. John Eaton Says:

    >We, as users, play a role because we have a responsibility to report bugs for >the good of all of us using the product.

    If you release your product under an opensource license then I will be glad to report all the bugs I find as well as checking in the bug fixes along with documentation and a test suite. I’m that kind of guy.

    But if you are selling your product then my responsibility ends when my check clears. I expect that you will pay for the QA and bug fixes and if I’m doing your QA testing then I want to see a check from you.

    Let’s start a movement. If IP vendors had to pay the going rate for all the QA testing that users perform then maybe they would do a better job before they release.

    John Eaton

  8. George Harper Says:

    Interesting piece — and good points. This is a completely self-serving comment (I run marketing at Bluespec for full disclosure), but I think there are two additional problems:

    1. RTL semantics cannot ensure proper connectivity, both in terms of port hookup and in terms of interface protocol — this means that designers have to lean on written specifications to understand the protocol and caveats around a piece of IP. It also means that a lot of control logic has to be written for every instantiation of a piece of IP. We use FIFO as the classic example — for every instantiation:
    * You have to ensure that you don’t enqueue when full; don’t dequeue when empty; and don’t simultaneously enqueue and dequeue when you are not supposed to (each FIFO is different) — this is a fair amount of control logic
    * If there are more than one user of the IP, you need to correctly coordinate this control logic and mux/arbitration logic with others — even more complicated

    2. Inevitably, and especially for in-house IP, you need to change something — this is where you break things because it’s hard to read other people’s RTL and because control logic is highly complex.

    I like the idea of reporting quality in public forum — but without a better semantic model for hardware, you’ll never solve the above two issues.

  9. Soft IP Says:

    Very Interesting Blog! Its agreed when procuring IPs from another company or Portals (such as design-reuse, chipestimate or IPsupermarket will be always tedious task. However you would be able to compare but again the quality of IP will be always an issue until and unless you’ve worked with that company.

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