A Tale of Two Booths - Certess and Nusym

I had successfully avoided the zoo that is Monday at DAC and spent Tuesday zig-zagging the exhibit halls looking for my target list of companies to visit. (And former EDA colleagues, now another year older, greyer, and heavier). Interestingly enough, the first and last booths I visited on Tuesday seemed to offer opposite approaches to address the same issue. It was the best of times, it was the worst of times.

A well polished street magician got my attention at first at the Certess booth. After a few card tricks, finding the card I had picked out in the deck, he told me that it was as easy for him to find the card as it was for Certess to find the bugs in my design. Very clever!!! Someone must have been pretty proud they came up with that one. In any case, I’d had some exposure to Certess previously and was interested enough to invest 15 minutes.

Certess’ tool does something they call functional qualification. It’s kinda like ATPG fault grading for your verification suite. Basically, it seeds your DUT with potential bugs, then considers a bug “qualified” if the verification suite would cause the bug to be controlled and observed by a checker or assertion. If you have unqualified bugs (i.e. aspects of your design that are not tested), then there are holes in your verification suite.

This is a potentially useful tool since it helps you understand where the holes are in your verification suite. What next? Write more tests and run more vectors to get to those unqualified bugs. Ugh….more tests? I was hoping this would reduce the work, not increase it!!! This might be increasing my confidence, but life was so much simpler when I could delude myself that my test suite was actually complete.

Whereas the magician caught my attention at the Certess booth, I almost missed the Nusym booth as it was tucked away in the back corner of the Exhibit Hall. Actually, they did not really have a booth, just a few demo suites with a Nusymian guarding the entrance armed with nothing more than a RFID reader and a box of Twinkies. (I did not have my camera, so you’ll have to use your imagination). After all the attention they had gotten at DVCon and from Cooley, I was surprised that “harry the ASIC guy” could just walk up and get a demo in the suite.

(Disclaimer: There was no NDA required and I asked if this was OK to blog about and was told “Yup”, so here goes…)

The cool technology behind Nusym is the ability to do on-the-fly (during simulation) coverage analysis and reactively focused vector generation. Imagine a standard System Verilog testbench with constrained random generators and checkers and coverage groups defining your functional coverage goal. Using standard constrained random testing, the generators create patterns independent of what is inside the DUT and what is happening with the coverage monitors. If you hit actual coverage monitors or not, it doesn’t matter. The generators will do what they will do, perhaps hitting the same coverage monitors over and over and missing others altogether. Result: Lots of vectors run, insufficient functional coverage, more tests needed (random or directed).

The Nusym tool (no name yet) understands the DUT and does on-the-fly coverage analysis. It builds an internal model that includes all of the branches in your DUT and all of your coverage monitors. The constraint solver then generates patterns that try to get to the coverage monitors intentionally. In this way, it can get to deeply nested and hard to reach coverage points in a few vectors whereas constrained random may take a long time or never get there. Also, when you trigger a coverage monitor, it crosses it off the list and know it does not have to hit that monitor again. So the next vectors will try to hit something new. As compared to Certess, this is actually reducing the number of tests I need to write. In fact, they recommend just having a very simple generator that defines the basic constraints and focusing most of the energy on writing the coverage monitors. Result: Much fewer vectors run, high functional coverage. No more tests needed.

It sounds too good to be true, but it was obvious that these guys really believe in this tool and that they have something special. They are taking it slow. Nusym does not have a released product yet, but they have core technology with which they are working with a few customers/partners. They are also focusing on the core of the market, Verilog DUT, System Verilog Testbench. I would not throw out my current simulator just yet, but this seems like very unique and very powerful technology that can get coverage closure orders of magnitude faster than current solutions.

If anyone else saw their demo or has any comments, please chime in.

harry the ASIC guy

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7 Responses to “A Tale of Two Booths - Certess and Nusym”

  1. Brad Says:

    Harry,

    I stopped by the Nusym booth on Monday and was pretty disappointed. I asked for literature and they didn’t have any. I asked the guy if he could tell me a little about his tool and he said he didn’t know anything and went to get another guy. I asked that guy if he could tell me about the tool and after a few moments of uncomfortable silence he asked if he could scan my badge and told me to come back later for a demo. I never made it back to their booth for the demo because I was booked the rest of the day.

    I hope their poor presentation means the company has hired more engineers to make the tool good rather than salesmen to sell it.

  2. harry Says:

    Brad,

    You’re right. As I mentioned, they did not have a booth, just the demo suites. Plus they’re just in the process of coming out of stealth mode, don’t have a finished product to ship, and are wary of competitors trying to sneak in to see the demo. Pretty typical for a company at their stage at DAC.

    You’re right with your last comment. The company was basically founded by engineers and the marketing manager is an engineer. All their focus right now is on getting the technology working, adding key features that their customers ask for and making their few customers successful. Then they’ll worry about pretty brochures.

    Personally, being a new media guy, I think the low-key engineer focused approach may work better than press releases, glossy success stories, and snazzy presentations. My advice to them would be to start a blog as their first marketing channel. The engineer who did our demo was very excited and passionate about this tool, so I’d suggest he start blogging about the cool things he’s accomplishing with this tool. Word will spread.

  3. Mark Hampton Says:

    Harry,

    Thanks for covering Certess here. There is one point I’d like to clarify, “unqualified bugs” do not only lead to more tests, they may identify problems like broken or insufficient checkers. The vectors are not worth much if the design’s behavior doesn’t get checked correctly.

    We see functional qualification as complimentary to the “intelligent testbench”. It is helping by identifying missing checkers and/or coverage monitors.

    Regards,
    Mark

  4. harry the ASIC guy Says:

    Mark,

    Thanks for the clarification. I have several people come up to me afterwards and speak well of Certess’ technology. I’d be glad to learn more. I’m sure we’ll be hearing more form your company, since it is actually doing something “new”.

    Harry

  5. Sean Murphy Says:

    Semifore has blogged about their use of Certess and how useful they found it to improve the quality of the test benches they generate to verify the register map that their csrCompiler generates. See http://www.semifore.com/blog/2008/11/20/semifores-experience-with-certess-certitude/

  6. Avidan Efody Says:

    Interestingly enough, Mentor has a tool which tries to do the same thing as Nusym but by analysing the generator instead of the coverage. The tool is called InFact and it creates a graph of all the possible generated data combinations, and then scans them in an orderly manner, to avoid repetitions. My impression is that both tools can help in well defined focus areas, but not for an entire design, where the number of possibilites defined by either coverage or generators is simply too big. But what do I know, I’m just a verification guy ;-), not a mathmatician…

    http://www.mentor.com/products/fv/infact/

  7. harry Says:

    Thanks Avidan. It should be interesting to see how far these tools have come in the last year, especially if NuSym is ready to promote their “technology” to a full-fledged product.

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