DVCon Survey Results – What Do They Mean?

I came across some interesting survey results from the 2007 and 2008 DVCon. Keep in mind, like with any survey, results are skewed based on attendees, which tend to be verification engineers who tend to be using the more advanced methods than the general population. Hence, I’d put more weight on the trends than on the absolute numbers.

1) Which is your primary design language?
                2007     2008
Verilog          56%      55%
VHDL              9%      10%
C/C++            13%      12%
SystemC           9%       8%
SystemVerilog    13%      15%

2 Which primary verification language do you use?
                2007     2008
C/C+             18%      18%
e                 7%       5%
OpenVera          4%       4%
Verilog          28%      25%
VHDL              7%       7%
System C         13%      11%
SystemVerilog    23%      30%

3) Which primary verification language do you plan to
use for your next design?
                2007     2008
C/C++            16%      15%
e                 5%       4%
OpenVera          1%       2%
Verilog          16%      16%
VHDL              4%       5%
SystemC          15%      11%
SystemVerilog    43%      47%

4) Which primary property specification (assertion-based
verification) language do you use?
                2007     2008
Verilog          31%      34%
VHDL              7%       6%
PSL              12%      10%
SVA              49%      50%


harry the ASIC guy

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7 Responses to “DVCon Survey Results – What Do They Mean?”

  1. Brad Pierce says:

    How could “Verilog” be the answer to question 4? — “Which primary property specification (assertion-based verification) language do you use?”

  2. Brad,

    I was wondering that myself. Only thing I could think was that people confused SVA and Verilog. Perhaps the same for VHDL?

    Come to think of it, I would have expected some % of people using no assertions at all.


  3. JohnB says:

    Interesting data. Thanks for sharing.

    Maybe using “Verilog” in #4 means using native Verilog assertions? “This shouldn’t happen, if it does, issue a message or corrupt the data.” Not quite what I’d formally call a property, but it is an assertion.

  4. harry says:

    The % of e and Vera users looks REALLY low. John Cooley’s 2007 DVCon numbers had over 40% using e or Vera. Same conference …. same attendees.

    What gives?

  5. Jeremy Ralph says:

    Seeing Verilog as a property specification language was a surprise to me too. I’m surprised there isn’t more VHDL for design and I’m really surprised to see the SV is higher for design than VHDL. It’s encouraging to see the SV numbers, but that may be because this is a Verification conference. I’d be interested to know what proportion of the SV is OVM vs. VMM.

  6. harry says:

    Jeremy et al,

    If you’d like to weigh in on the verification methodology question, you can vote (anonymously) at the following link.

    I’d love to see if we can get more respondents online than DVCon in person. That would be really cool.


  7. Jim Lewis says:

    Not surprising results since at this point DVCon is irrelevant to people using a VHDL only verification methodology. The conference does not have any significant VHDL papers since the program committee rejects them, so how would someone justify attending?


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