Archive for January, 2009

DVCon Survey Results – What Do They Mean?

Tuesday, January 27th, 2009

I came across some interesting survey results from the 2007 and 2008 DVCon. Keep in mind, like with any survey, results are skewed based on attendees, which tend to be verification engineers who tend to be using the more advanced methods than the general population. Hence, I’d put more weight on the trends than on the absolute numbers.

1) Which is your primary design language?
                2007     2008
Verilog          56%      55%
VHDL              9%      10%
C/C++            13%      12%
SystemC           9%       8%
SystemVerilog    13%      15%

2 Which primary verification language do you use?
                2007     2008
C/C+             18%      18%
e                 7%       5%
OpenVera          4%       4%
Verilog          28%      25%
VHDL              7%       7%
System C         13%      11%
SystemVerilog    23%      30%

3) Which primary verification language do you plan to
use for your next design?
                2007     2008
C/C++            16%      15%
e                 5%       4%
OpenVera          1%       2%
Verilog          16%      16%
VHDL              4%       5%
SystemC          15%      11%
SystemVerilog    43%      47%

4) Which primary property specification (assertion-based
verification) language do you use?
                2007     2008
Verilog          31%      34%
VHDL              7%       6%
PSL              12%      10%
SVA              49%      50%

Thoughts?

harry the ASIC guy