Verification Methodology Poll Results

Last week I initiated a poll of verification methodologies being used for functional verification of ASICs. Unlike other polls or surveys, this one was done in a very “open” fashion using a website that allows everyone to view the raw data. In this way, anyone can analyze the data and draw the conclusions that make sense to them, and those conclusions can be challenged and debated based on the data.

What happened next was interesting. Within 48 hours, the poll had received almost 200 responses from all over the world. It had garnered the attention of the big EDA vendors who solicited their supporters to vote. And, as a result, had became a focal point for shenanigans from over-zealous VMM and OVM fans.  I had several long nights digging through the data and now I am ready to present the results.

As promised, here is the raw data in PDF format and as an Excel workbook. The only change I have made is to remove the names of the individual 249 respondents.

In summary, the results are as follows:

RAW Results from Verification Methodology Poll


(Note: The total is more than the 249 respondents because one respondent could be using more than one methodology.)

Regarding the big 3 vendors, the data shows a remarkable consistency with Gary Smith’s market share data. There are 85 respondents planning to use the Synopsys methodologies (VMM,RVM, or Vera) and there are 150 respondents planning to use the Mentor or Cadence methodologies (OVM, AVM, eRM, e). That represents 36% for Synopsys and 64% for Mentor/Cadence. Gary’s data shows Synopsys with 34% market share, Mentor with 35%, and Cadence with 30%.

Methodology Split

Gary Smith Market Share Data


I’ll share some more insights in upcoming posts. In the meantime, please feel free to offer any insights that you have through your comments. Remember, you too have access to the raw data. This invitation includes the EDA vendors. And feel free to challenge my conclusions … but back it up with data!

harry the ASIC guy

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6 Responses to “Verification Methodology Poll Results”

  1. Jeremy Ralph Says:

    Harry, you’ve put a lot of work into this. Interesting that the results align with Gary Smith’s market share reports, which is likely no coincidence.

    Since the big EDA vendors “solicited their supporters to vote,” I wonder if that causes the native SV camp to be under represented and the *VMs to be over-represented.

  2. harry Says:

    Hi Jeremy,

    It’s hard to say. One could speculate that indeed the native SV is under-represented, as well as native verilog and VHDL. Seeing as this poll was likely to hit those who are early adopters, that would make sense.

    I need to also point out that there was no category for SystemC/C/C++ which was my oversight. I received a few comments that this was missing and it seems those people voted in “other”.

    Harry

  3. GopiKrishna Says:

    On what bases should I consider word “Market share” ? based on the number of users or based on the Number of companies.

  4. Brian Says:

    SystemC is neglected?

  5. harry Says:

    Hi Brian,

    Yeah, that was my oversight at the time. I think it’s grown in popularity due to TLM 2.0 since I did this survey almost 2 years ago, so I’d want to include it today.

    Thanks,

    Harry

  6. harry Says:

    Hi Brian,

    Yeah, I had left it out by mistake. I think it’s grown in popularity due to TLM 2.0 since I did this survey almost 2 years ago, so I’d want to include it today.

    Thanks,

    Harry

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