I started my career in the 70’s and have seen huge changes in how we design chips. My first couple of decades I used schematic capture systems.

Todays asic designs are incredible. The size, speed,complexities and schedules are mind numbing. Every couple of years we get a new process that adds new requirements on top of previous ones. Nothing in my experience as an R+D engineer has prepared me for this.

I have however spent a couple of stints in manufacturing bringing new products up the product ramp. Those experiences have helped me deal with todays asic design issues.

The traditional R+D methodology is to put together a team of really smart people to create the one prototype and then throw it over the wall to production. That doesn’t work anymore. What works is to design a process that takes input from designers and “builds” a asic maskset in the same manner that you do high volume production.

Lynx is one such process. You can’t look at it as a R+D tool but rather as a production tool.

Every piece that is used on a production line has a parts spec that fully describes it and an incoming inspection procedure that tells you how to verify that the part coming in the door met that spec.

Does lynx have a spec that lists the requirements for the incoming RTL and constraint files? How do you check the rtl to verify that it is correct?
What do you do if it’s not?

Does lynx support “Just-in-time” delivery? In production it means that the parts arrive only when they are needed and you don’t store up any WIP
(work-in-progress) material. That way if there is a problem then there is less rework to deal with.

In asic design this means when a designer makes a mistake you catch it quickly. It doesn’t take a month to synthesize into a netlist only to be caught by some back end tool. How long does it take you to catch errors?

John Eaton