I hear so often nowadays that FPGAs are the new ASICs. So I decided to take off half a day and attend a Synopsys FPGA Seminar just down the street from where I’m working (literally a 5 minute walk). I would like to share some observations as an ASIC guy amongst FPGA guys and gals.
Observation #1 - FPGA people put their pants on one leg at a time, just like me. (Actually, I sometimes do both legs at the same time, but that’s another story). I had been led to believe that there was some sort of secret cabal of FPGA people that all knew the magic language of FPGAs that nobody else knew. Not the case. Although there is certainly a unique set of terminology and acronyms in the FPGA arena (LUTs, DCM, Block RAM) they are all fairly straightforward once you know them.
Observation #2 - I thought that behavioral synthesis had died, but apparently it was just hibernating. There is behavioral synthesis capability in some of the higher-level FPGA tools. I’ve never used it, so I can’t say one way or the other. But it sure was a blast from the past (circa 2000). Memories of SPW, Behavioral Compiler, Cossap, Monet, Matisse.
Observation #3 - Physical design of FPGAs is getting like ASICs. There are floorplanning tools, tools that back-annotate placement back into synthesis, tools that perform synthesis and placement together, tools for doing pre-route and post-route timing analysis. Made me think of Floorplan Manager, Physical Compiler, and IC Compiler.
Observation #4 - Verification of FPGAs is getting like ASICs. It can take a day to resynthesize and route a large FPGA to get back in the lab debugging. That’s an unacceptable turnaround time for debugging an FPGA with lots of bugs. Assertions (SVA, PSL), high-level verification languages (System-Verilog / OVM / VMM) and cross domain checkers are methods being stolen from the ASIC design world to address large FPGA verification. The trick is deciding when there has been enough simulation to start debug in the lab.
After this session, I think this ASIC guy is going to feel right at home in the FPGA world of the future.
harry the ASIC guy