One good thing the FPGA co’s have going for them is the embedded system development kits like Xilinx Platform Studio (XPS) & Embedded Development Kit (EDK). Altera has SOPC builder and the NIOS II IDE. These make it pretty easy to take a processor, bolt on IP and even create custom peripherals (with http://spectareg.com derived register maps) and create a custom and powerful embedded system and prototype it quickly and cost effectively. Within less than a day of first picking up the Xilinx board/tools I was able to have a Xilinx microblaze embedded system up and prototyping. This had a custom peripheral mapped onto the bus, with custom software running on the microblaze. Altera’s NIOS kits are just as easy if not easier to work with too.

Here are some more: ISE, EDK, XPS, DSP48, CLB, GTX, GTP, CMT, GSR, MGT, DCI

An interesting set of observations. Tools like Behavioral Compiler have not really gone into hibernation, just slowly evolved into Algorithmic Synthesis tools like our own PICO Extreme FPGA (www.synfora.com).

We are seeing that the level of interest in these kinds of tools is on the rise as more people are shifting computationally heavy apps from ASIC to FPGA for cost/performance/volume reasons. Besides getting your design down on the FPGA faster than writing Verilog/VHDL by hand, the verification side of things is also greatly improved by Algorithmic Synthesis. There is no comparison between the number of vectors you can cheaply test using a C compiler vs an expensive RTL simulator.

The reason for seeing a bigger push for this technology out of FPGA teams is that they are more software based — i.e.
Verilog/VHDL appears to be an arcane and complex language — why would anybody program using that. So we see more emphasis on making it easier for the DSP programmer to get to FPGA hardware whereas in ASIC, you are normally talking to RTL engineers who are trying to move into C.

Given the difference between FPGA/ASIC markets, we expect FPGAs to be the driving application for algorithmic synthesis over the next five years.

Another well-known site about FPGA is http://fpgablog.com/.

Great to discuss with you about the difference between ASIC/FPGA devel. Actually it’s not easy to find right persons to discuss this topic.

John, actually FPGA designer don’t care about DFT. Vendors do it with the “raw” FPGA chip before shipping to users (here users are FPGA developers). Most likely FPGA developers are working with fault-free FPGA chip and only program it with the custom design. Today’s most FPGAs are implementing logics with SRAM-based LUT followed by MUX and DFF.

FPGA guys prefer VHDL to Verilog, because usually FPGA developments are more sensitive to the cost of EDA tools as well as TTM, somewhat Verilog need more carefulness or more tools (for linting). But all these are not critical issues for experienced designers.

FPGA designers have to care much more about speed performance and resource utilization than ASIC’s, especially the ASIC designers who began their job recently. When I was working in a SoC project, some codes came from FPGA designers and some from typical ASIC designers. The differences are huge. The sense is bit like assembly vs. C program. I saw that a piece of VHDL codes from ASIC designer has a “process” with 8000+ lines!

Hi Jeremy, I visited your web and you’re providing a great tool! We have a similar in-house tool by Tcl and Python, with less bus standards support.

Because of in-system reconfigurability, FPGA design is more like software: it will never be completed, it’s just released. FPGA design may be released for system testing at very early stage. But it doesn’t mean simulation is less important for FPGA design — it’s easy to find there is a bug but difficult to address and fix it.

Earlier this week I attended Xilinx XTech in Vancouver, Canada. For a town that has relatively few ASIC cos. there is a lot of FPGA action. Interestingly, most ASIC companies we talk to about our http://SpectaReg.com register-map automation solution immediately know what we are talking about, but the FPGA types (aside from some high-performance FPGA-based developers) don’t really get it until we explain.

Coming from an ASIC world where designs are much more complex and must be fully verified before “tape out” is a slightly different way of thinking. Since our product is used by both FPGA and ASIC users, I get a good view into both worlds. FPGAs flows are relatively similar at the front end but in general are simpler. One of the main differences I notice is that FPGA developers prefer to prototype in the lab rather than verify. FPGA developers are much more gate limited, so they try and squeeze as much as they can into a set fabric. Also, it seems that FPGA developers use VHDL more than the ASIC world and expect their tools to be much cheaper than ASIC tools.

Comment: Putting you pants on two legs at a time? YouTube material, really.

Question: (Maybe daryl can comment on this) What is DFT to a FPGA designer? Is it any different than in the ASIC world? Does it exist?

Thanks,
JMF

Thanks for your comments. I’m fortunate to have knowledgeable and articulate readers like you that provide insight on topics like these of which I am less familiar.

Harry

I think because architectures are so varied the silicon vendors have had to collaborate more deeply with tool suppliers, and because Xilinx and Altera effectively split the market in a way that no supplier or pair of suppliers dominate ASIC, FPGA’s are taking a different path for industry evolution.

Especially in lower volume applications that make it more difficult to amortize mask costs and in software intensive applications where the prototypes are available immediately for test and debug (and iteration don’t involve a new mask set) the total cost of an FPGA solution compares favorably with ASIC/SOC approaches.

Three other good sources of information:

The FPGA Journal http://www.fpgajournal.com does a good job as a specialty on-line publication covering the space.

The annual “International Symposium on Field Programmable Gate Arrays” that’s held in Monterey (the University of Trier has a good recap of the last 15 years of topics/papers presented at http://www.informatik.uni-trier.de/~ley/db/conf/fpga/index.html ).

The European conference “FPGA World” http://www.fpgaworld.com/