Oasys or Mirage?

Oasis BMP

That’s the question that everyone was asking last week when Oasys Design Systems came out of stealth mode with a “chip synthesis” tool they claim leaves Synopsys’ Design Compiler and other synthesis tools in the dust. According to Sanjiv Kaul, Chairman of Oasys and former VP of Synopsys’ Implementation Business Unit, RealTime Designer can synthesize full chips up to 100 million gates in a single run, and do so 20x faster with smaller memory requirements and achieving better quality of results. Oh, and it also produces a legalized cell placement that can be taken forward into detailed routing.

Well, I had 3 different reactions to these claims:

1. “Too good to be true!”

This was also the most common reaction I heard from fellow designers when I told them of the Oasys claims. It was my own reaction a month or so ago when I first spoke to Oasys about their technology. (To tell the truth, I was wondering what they were smoking.) Paul McLellan, as of last week a blogger for Oasys, indicated that disbelief was the most common reaction heard from people Oasys talks to about this product. Steve Meier, former VP of R&D for IC Compiler at Synopsys, said the same thing on Twitter and added some specific questions for Oasys to answer. Even one of the Oasoids (is it to early to coin that phrase) acknowledged to me privately that he was incredulous when he was first approached months ago to join the team. I guess he was convinced enough to join.

2. “I’ve seen this movie before, and I know how it ends.”

That was my second reaction. After all, there were Synopsys killers before. Ambit (out of which, by the way, came most of the developers of the Oasys tool) was the first big threat. They had a better QOR (quality of results) by many accounts, but Synopsys responded quickly to stave them off. Then came Get2Chip. Similar story. Cadence’s RTL Compiler, which combines technology from both Ambit and Get2Chip, is well regarded by many but still it has a very small market share. Bottom line, nobody ever got fired for choosing Design Compiler, so it’s hard to imagine a mass migration. Still, if the Oasys claims are true, they’d have a much more compelling advantage than Ambit or Get2Chip ever had.

3. “Synthesis? Who cares about synthesis?”

That’s my third reaction. Verification is the #1 problem for ASIC design teams. DFM is a critical issue. ESL and C-synthesis are starting to take off. RTL synthesis addresses none of these big problems or opportunities. It’s a solved problem. Indeed, many design flows just do a “quick and dirty” synthesis in order to get a netlist in to place and route where real timing can be seen and a good placement performed. I hear very few people complaining about synthesis, so I wonder who is going to spend money in a tight economy on something that just “ain’t broken”. True, synthesis may be a bottleneck for 100M gate ASICs, but how many companies are doing those and can those companies alone support Oasys. If you talk to Oasys, however, they feel that the availability of such fast synthesis will change the way people design, creating a “new platform”. I’m not sure I see that, but perhaps they are smarter than me.


OK, so that’s my first 3 thoughts regarding Oasys design. I’ll be getting a better look at them at DAC and will share what I learn in some upcoming blog posts. Please feel free to share your thoughts here as well. Between us, we can hopefully decide if this Oasys is real or a mirage.

harry the ASIC guy

1 Star2 Stars3 Stars4 Stars5 Stars (No Ratings Yet)
Loading ... Loading ...

Tags: , , , , ,

10 Responses to “Oasys or Mirage?”

  1. Sean Murphy Says:

    Synthesis is certainly an issue, and dramatically faster synthesis with significantly higher capacity would find a market. Three other examples of breakthrough EDA products that were at first met with disbelief (perhaps you can think of some others):

    1. Synplicity’s synthesis solution for FPGA’s was dramatically faster and revolutionized the industry

    2. Mentor’s Calibre unseated Dracula as the incumbent for DRC

    3. Chronologic changed the rules for Verilog simulation.

    There is a serious group of folks around Oasys who have put their own money in, not VC money, who have long track records in EDA. It’s certainly possible that they are mistaken. But if they roll out other customer announcements in the next weeks to months then it’s likely that there will be a realignment in the synthesis market. The Design Compiler architecture is more than 20 years old, we are now approximately ten generations of chips past where they entered the market. It’s not proof that DC may be obsolete, but it certainly allows for the possibility.

    Let me ask you a different question: at what point does the DC architecture give out? Would you expect to be using it 20 years from now?

    Your observations boil down to

    1. it’s not true (my interpretation of “too good to be true”)
    2. it won’t make a difference
    3. it really doesn’t matter

    I would suggest that a strong alternative will put both price and performance pressure on Synopsys. Even at 15-25% market share Oasys can have a significant impact on how fast DC improves its capacity and runtime, which will benefit anyone using it. I think it’s more likely than many accounts will run them in parallel, both to keep a credible threat of switching more business and to get the best new features out of both vendors: making it a “horserace” again benefits all DC users.

    Two questions:

    1. At the runtimes they are talking about (e.g. 20 minutes for an SOC), and the size of the input and output files, it could be offered as a SaaS option. Would that make it more revolutionary?

    2. What would constitute unambiguous proof in your mind that it was a breakthrough product?

  2. harry Says:

    Hi Sean,

    My analysis was meant to represent a healthy skepticism, not a conclusion that this technology is not real. Indeed, this will probably be the most interesting battle in quite a while in EDA, moreso even than the OVM/VMM battle of a year ago.

    1. Regarding whether this is too good to be true or not, one needs to take a design through the rest of the physical design process to see if the results are truly better afterwards. That means CTS, detailed routing, signal integrity checks and fixes, etc. It’s one thing to produce a placed gates design and it’s another to produce one that will result in good QoR. All we have now is a press release and maybe some more customer announcements coming up. It would be great to run a real benchmark with an open source design using both tools.

    2. Regarding whether there is market share to be taken, I think that depends. As I acknowledged, neither Ambit or Get2Chip had the kind of advantage that Oasys claims. Still, if Synopsys can respond, as they have in the past, with on par or better QOR, Oasys will have a hard sell, even at 20x runtime advantage.

    3. Regarding who cares about synthesis, there are the large bleeding edge customers and they are willing to spend money for value. I’m sure they will be Oasys’ first foothold.

    As for a SaaS solution, that is an interesting thought. I think there is still quite a bit of data to transfer, but it could be doable.

    As for unambiguous proof, there is only one thing, tapeout success at 45nm and below.

  3. John MacDonald Says:

    Fast, large synthesis could no doubt help get a design ready for implementation. Invariably, a number of iterations are necessary just to get a design cleaned up for test insertion and physical design. However, once it’s ready to go, the first stop after synthesis should be formal verification. The capacity of synthesis tools on the market already exceed the capacity of formal verifiers, particularly if the design contains a significant number of operators common in signal processing algorithms. Best practice is to synthesize hierarchical blocks per implementation. Plan top down, implement bottom up.

  4. harry Says:

    Hi John,

    Thanks for the comment and good luck with your Chip 101 site.

    For what it’s worth, Oasys claimed during their conference call that they have run formal verification on the benchmark designs. I don’t know if these designs had a lot of arithmentic blocks (I know multipliers can be a real issue for formal verification). Still, your point is very valid. The methodology issues need to be understood as well as the tool issues, a point made by someone else I spoke to today.


  5. danubi1 Says:


    IMHO, the real benefit of being able to synthesize huge designs without partitioning is to help with ‘planning top down’, as John put it. I can see that being valuable in the prototyping part of the flow. Remember what Silicon Perspective did to floorplanning circa 2001? Yes, their placement was probably not the best you could get for timing closure, but for the fast turns on large designs required to create a physical prototype, they were hard to beat.

    Oh.. logical equivalency checking is pretty powerful these days.. Lots of smart algorithms for handing large datapath operators..

  6. Denis Says:

    Cadence’s share of the logic synthesis market is “very small”? Where do you get your numbers? Just how big is the logic synthesis market these days and what is Cadence’s share?

  7. harry Says:

    Hi Denis,

    Gary Smith published market share numbers for 2006 that showed Cadence with 10% market share, which I consider “very small”. I doubt this has changed much since then.


  8. Denis Says:

    I see a quote from Gary Smith in early 2008 saying that “DC is losing synthesis market share.” I hate to admit this is from deepchip, but here’s the link:

    Your own source contradicts you.

  9. Jack Erickson Says:

    In Gary Smith’s defense, synthesis market share is difficult to measure because a lot of physical design teams are running RTL Compiler to optimize DC netlists so they can close in physical. This is likely not counted, but it is prevalent.

    But Denis is correct, and all you have to do is look at the amount of customers that have publicly endorsed RTL Compiler: http://www.cadence.com/products/ld/Pages/rconline.aspx

    What we’re seeing is that if folks want to close on their design goals in time, they are going to have to consider more modern technology, whether it be RTL Compiler, Oasys, or somebody we haven’t heard of yet.

  10.   Is it too good to be true? STARC says it’s for real by Oasys Says:

    […] noticed and gives a good summary of the product. HarryTheAsicGuy has covered the announcement with the expected skepticism: the results are too good to be true, […]

Leave a Reply