But Denis is correct, and all you have to do is look at the amount of customers that have publicly endorsed RTL Compiler: http://www.cadence.com/products/ld/Pages/rconline.aspx

What we’re seeing is that if folks want to close on their design goals in time, they are going to have to consider more modern technology, whether it be RTL Compiler, Oasys, or somebody we haven’t heard of yet.

Your own source contradicts you.

Gary Smith published market share numbers for 2006 that showed Cadence with 10% market share, which I consider “very small”. I doubt this has changed much since then.

Harry

IMHO, the real benefit of being able to synthesize huge designs without partitioning is to help with ‘planning top down’, as John put it. I can see that being valuable in the prototyping part of the flow. Remember what Silicon Perspective did to floorplanning circa 2001? Yes, their placement was probably not the best you could get for timing closure, but for the fast turns on large designs required to create a physical prototype, they were hard to beat.

Oh.. logical equivalency checking is pretty powerful these days.. Lots of smart algorithms for handing large datapath operators..

Thanks for the comment and good luck with your Chip 101 site.

For what it’s worth, Oasys claimed during their conference call that they have run formal verification on the benchmark designs. I don’t know if these designs had a lot of arithmentic blocks (I know multipliers can be a real issue for formal verification). Still, your point is very valid. The methodology issues need to be understood as well as the tool issues, a point made by someone else I spoke to today.

Harry

My analysis was meant to represent a healthy skepticism, not a conclusion that this technology is not real. Indeed, this will probably be the most interesting battle in quite a while in EDA, moreso even than the OVM/VMM battle of a year ago.

1. Regarding whether this is too good to be true or not, one needs to take a design through the rest of the physical design process to see if the results are truly better afterwards. That means CTS, detailed routing, signal integrity checks and fixes, etc. It’s one thing to produce a placed gates design and it’s another to produce one that will result in good QoR. All we have now is a press release and maybe some more customer announcements coming up. It would be great to run a real benchmark with an open source design using both tools.

2. Regarding whether there is market share to be taken, I think that depends. As I acknowledged, neither Ambit or Get2Chip had the kind of advantage that Oasys claims. Still, if Synopsys can respond, as they have in the past, with on par or better QOR, Oasys will have a hard sell, even at 20x runtime advantage.

3. Regarding who cares about synthesis, there are the large bleeding edge customers and they are willing to spend money for value. I’m sure they will be Oasys’ first foothold.

As for a SaaS solution, that is an interesting thought. I think there is still quite a bit of data to transfer, but it could be doable.

As for unambiguous proof, there is only one thing, tapeout success at 45nm and below.

1. Synplicity’s synthesis solution for FPGA’s was dramatically faster and revolutionized the industry

2. Mentor’s Calibre unseated Dracula as the incumbent for DRC

3. Chronologic changed the rules for Verilog simulation.

There is a serious group of folks around Oasys who have put their own money in, not VC money, who have long track records in EDA. It’s certainly possible that they are mistaken. But if they roll out other customer announcements in the next weeks to months then it’s likely that there will be a realignment in the synthesis market. The Design Compiler architecture is more than 20 years old, we are now approximately ten generations of chips past where they entered the market. It’s not proof that DC may be obsolete, but it certainly allows for the possibility.

Let me ask you a different question: at what point does the DC architecture give out? Would you expect to be using it 20 years from now?

Your observations boil down to

1. it’s not true (my interpretation of “too good to be true”)
2. it won’t make a difference
3. it really doesn’t matter

I would suggest that a strong alternative will put both price and performance pressure on Synopsys. Even at 15-25% market share Oasys can have a significant impact on how fast DC improves its capacity and runtime, which will benefit anyone using it. I think it’s more likely than many accounts will run them in parallel, both to keep a credible threat of switching more business and to get the best new features out of both vendors: making it a “horserace” again benefits all DC users.

Two questions:

1. At the runtimes they are talking about (e.g. 20 minutes for an SOC), and the size of the input and output files, it could be offered as a SaaS option. Would that make it more revolutionary?

2. What would constitute unambiguous proof in your mind that it was a breakthrough product?