Aldec, Inc. now provides Riviera-PRO™: a simulator supporting OVM (Open Verification Methodology) and UVM (Universal Verification Methodology).

The simulator is able to handle the most advanced verification and debugging technologies at levels ranging from RTL to ESL: Transaction-Level Modeling, Assertion-Based Verification, Constrained Random Test, Functional and Code Coverage, etc. The latest release supports the Open Verification Methodology, providing pre-compiled libraries for OVM 2.1.1, 2.0.3 and UVM 1.0. The OVM methodology aids engineers in developing reusable, interoperable verification IP and create re-configurable, hierarchical environments that facilitate “plug-and-play” approach to creation of high-level testbenches. Riviera-PRO users can turn on all available optimizations to achieve maximal simulation speeds, or use advanced design analysis and debugging features to quickly hunt bugs that managed to sneak into their projects. The tool uses separate compilation and simulation approach, and can be controlled from the console, scripts or via flexible yet powerful GUI.

Riviera-PRO provides full mixed language simulation, including standard VHDL, Verilog®, SystemVerilog, SystemC/C/C++ language support. It comes with an optimal waveform toolset, ultra-fast debugging tools, code coverage, and includes our high-speed mixed-language simulation engine. Riviera-PRO has methodologies for Advanced Verification Inside; such as ESL, TLM, OVM, VMM and Assertion-Based Verification (ABV) methodologies Riviera-PRO is enabled for HES™, Hardware Embedded Simulation technology, for significant boost of performance, including emulation, acceleration and prototyping. Riviera-PRO 2010.06 is a multi-platform Simulator, supporting Windows® 7, Vista and XP – both 32 and 64 bit, and Linux 32/64 bit operating systems.

Product Information: http://www.aldec.com/products/rivierapro

In that same post Coudert asserts that the Oasys architecture is based on And Inverter Graph paradigm http://en.wikipedia.org/wiki/And-inverter_graph (see for example http://www.eecs.berkeley.edu/~alanmi/abc/ ) so Synopsys should be able to incorporate similar technology into DC.

The real issue is whether, after twenty five years of evolution, the DC architecture is being obsoleted by Oasys. That will likely take 3-5 years to see but Oasys appears to have at least achieved a “co-existence” strategy where customers would do well to buy one license. Because of anti-trust concerns Synopsys cannot mandate that 100% of EDA purchases be from them (it’s called a tied sale). In the near term it could be that Cadence’s offering collapses since it used to serve that purpose.

So I would say we are least in phase two of a potential market transition, where a new entrant has demonstrated viability and staying power. Given that they have not taken VC, they can contemplate a sustained campaign (vs. being six or eight years into a ten year fund that would soon start to force an exit). If they force Synopsys back to the drawing board for a better DC architecture that alone is an overdue benefit for EDA customers.

Thanks for keeping me honest. I can always count on you for that

My comments regarding Oasys for ASIC have nothing to do with the technology and everything to do with the industry. For all I know (and I have not used Oasys, so I don’t know first hand) they may have a tool that does everything they claim. Still, how many companies / design teams are looking to do a point tool replacement for logic and physical synthesis? There are some at the high end (Juniper, Renesas) but I don’t think it’s the big headache right now.

Honestly, I hope that I’m wrong and Oasys can challenge Big Purple. It would be nice to see some competition in an area that has been monopolized for 20 years.

- harry

Missed your post by a day. I agree that Oasys will make Xilinx’ synthesis much faster, and that will please the FPGA design crowd used to the “design => synthesize/place&R => debug => fix error => synthesis/P&R” loop described by your friend. I would also say that Oasys’ technology will make RTL-to-gate verification much better (see what I wrote there http://bit.ly/bSgpjb).

As for the $ aspect, FPGA synthesis tools provided by EDA may suffer a bit from the partnership, but that’s really up to them to show they can match or better Oasys’ tool. As far as I know, customers pay for Altera’s Quartus II, Synospys’ Synplify, and Mentor’s Precision because it produces better results, period. Whether that market is large enough to sustain all the players, that’s a different question. I am more concerned about Xilinx and Altera’s huge investment in their tools, which dwarf most of what EDA companies can afford for their FPGA solutions.

– Olivier

I have no inside information on the Xilinx Oasys deal but I would have to believe that Xilinx is paying Oasys something to have them support their product line. So an ASP of $0 is probably not accurate.

So now Oasys has endorsed offerings both for ASIC and FPGA and is competing against Synopsys synthesis offerings across the board.

Harry: what would it take to get you to re-assess? I admit I put them in the category of “interesting if true” earlier, but with two significant deals in different segments they appear to demonstrating staying power, if not growth. This gives users one solution for both, what other vendor offers that?

At some point they have to be taking share from Synopsys and Cadence. In fact that mile marker may already be in the rear view mirror, perhaps at EDA361 or EDA362?

This move does not surprise me at all. We have quite a few FPGA users, and not just mil/aero. Many folks in the networking segment are using FPGA as well.

There has been a trend during the past few years away from simple “burn-and-churn” development for FPGA to a more rigorous verification flow even as the synthesis and floor planning for FPGA move deeper into the FPGA vendor’s domain. We’ve seen that at the high-end and I hear that Aldec is seeing that in the middle-tier FPGA space as well. When you add to this the shift from Windows to Linux and the use of more and more design and verification IP, you can see FPGA development moving right into the EDA360 spotlight.

=Adam Sherer, Cadence