(Part 2 in the series Which Direction For EDA: 2D,3D, or 360?)
“Well, it just so happens that your friend here is only mostly dead. There’s a big difference between mostly dead and all dead.” - Miracle Max to Inigo Montoya, The Princess Bride
In the film The Princess Bride, Westley lies motionless and apparently dead on a table in the cottage of Miracle Max. After some complaining from Max and nagging from Max’s wife, Max devises a chocolate covered Miracle Pill that revives the mostly dead Westley so he can save his true love Buttercup from the evil Prince Humperdink.
In our story, 2D scaling is the mostly dead Westley, the semiconductor manufacturers are Miracle Max trying to create a Miracle Pill, and Gordon Moore is Buttercup waiting to be rescued. (I’m not sure who’s Prince Humperdink and Max’s wife, but if you have an idea, please let me know.)
Moore’s law (the colloquial term for 2D scaling) states that certain metrics of semiconductor technology performance proceed at a rate of approximately 2x every 2 years. It can refer to transistor size (channel length), density (gates / sq. mm), cost ($/gate), power (nA/gate), capacity (gates), or a combination of these. Indeed, over the last 2 decades we can draw a pretty straight line curve (log scale) to track the progress of these various metrics. Here is one such curve below that Michael Keating presented at SNUG 2010:
To be sure, achieving Moore’s law has not just been a matter of driving down the scaling road with the top down and the tunes on. There have been numerous roadblocks in the past that could have ended the trip, but we’ve always been able to find a detour or new road to keep the trip on schedule. Some are emboldened by our previous innovations and say “yeah, they’ve predicted the end of Moore’s law before and we always find a new way.” Others say that this time is different, that we are hitting barriers of physics; that we are running out of road to drive and will need to find a new means of transportation altogether. So, let’s look at some of these barriers and what may be able to get us beyond.
Most silicon-based semiconductors are produce with light that has a wavelength of 193nm, which is 4x the length of the minimum feature size of the current 45nm production technology. That does not seem possible, but tricks such as optical proximity correction (OPC) actually allow this to work. However, according to most experts in this field, those techniques will fail to work well very soon and new techniques will be needed.
Immersion Lithography is already in use (e.g. TSMC 45nm) and likely be needed starting at 32nm. Rather than air between the lens and the wafer, a liquid (currently very pure water) with an index of refraction > 1 is used to focus the beam and achieve smaller feature sizes. As you can imagine, this is not a simple process extension since the water needs to be contained, free of air bubbles, and then cleaned up without damaging the wafer or interfering with other aspects of the process. It can be done, but adds to the cost.
Double patterning is another technique currently in use and which will likely be required starting at 22nm. Instead of shrinking the patterns on the reticle to smaller feature sizes, the wafer is exposed to two (or more) different reticles each offset from the other to achieve a net effect of smaller feature size. After each exposure the wafer is etched, so this increases the number of process steps and hence the cost as does the need for multiple reticles for each layer.
Beyond 22 nm will likely require using a smaller wavelength of light. Extreme Ultraviolet (EUV) has a wavelength of 13.5nm and will likely take us to the 4nm node, but this technology is just now under development and production solutions may be very expensive when commercialized. Bernard Meyerson of IBM recently cited the cost of one such machine as $100M.
One technique that may actually reduce cost is called Electron-Beam Direct Write (EBDW), which is based upon traditional E-beam lithography that has been around since the early 1990s. Instead of using an optical reticle to define the patterns to be exposed on a wafer, E-beam lithography uses an electron beam to draw features on the wafer directly. This technology can be much more precise in feature size than optical methods, but is slower since the beam needs to traverse the entire wafer. Methods are being developed to utilize a massive number beams to speed up processing. Previous E-beam systems were very expensive and these will be no exception; on the other hand, there will be cost savings up-front since no masks are needed for EBDW. Another benefit - shorter fab runs will be more economically feasible since there won’t be as large an upfront cost for the masks to amortize.
There are some other next-generation lithography approaches being considered that you might wish to look at. All these approaches have been proven to some extent but some will require much more refinement to be technically and cost effective. Given our resourcefulness in the past, it’s likely that one or more methods will emerge to allow us to reach the 4nm node in about 12 years. But that may be the end of the line. As Michael Keating noted at SNUG this year, at 4nm you’re switching 3 electrons, so it does not seem you can get much further without some advancements in transistor design.
Next Blog Post: Is 2D Scaling Dead? - Looking at Transistor Design
harry the ASIC guy