My apologies for the recent hiatus in my blog posting. It’s been a difficult time personally for me the past few months, dealing with family illnesses. Hopefully, I can get it going again.
With all that I had going on, it was a relief to escape last week for a few days to DAC in San Diego. After several years attending as a blogger (what DAC calls “independent media”), it was exciting to be on the floor representing Xuropa at the Synopsys Cloud Partners Booth. I still got to see several friends like JL Gray, who wrote up what he heard from us, and Peggy Aycinena, who accused me of being a sellout since I was in the Synopsys Cloud booth and had a Synopsys badge lanyard. And of course, what DAC would be complete without Eric Thune of AtopTech telling me that cloud will never work for EDA.
One of the downsides of being in the booth was not being able to attend a lot of the other sessions. I missed The Woz, and the Logan & McLellan show, and Gary Smith, and a lot of the panel discussions. I was, however, able to sneak away for the EDA Cloud Computing Panel discussion, featuring the usual suspects and a few new ones. A highlight was when John Bruggeman of Cadence offered to buy John Chilton of Synopsys a beer at the Denali Party and work out a joint Synopsys/Cadence solution on the cloud. No word yet how that turned out. Another highlight was the audience poll at the end where 1/3 of the audience felt that most of EDA would be on the cloud in 3 years. I don’t know if this is correct or not, but this is the 3rd year we had a cloud panel at DAC, and each year the expectations increase. Richard Goering has a good writeup on the panel.
One booth I did visit and get an interesting demo was Duolog. Duolog is a Xuropa customer (you can try out their tool here), which is why I knew a little about them going in. They have a tool called Socrates Bitwise that does register management for processor based designs. In this tool, you specify all the processor accessible registers, their type (RO, RW, etc), the locations (base and offset), and the tool automatically generates the RTL, verification code (OVM, UVM, etc), register package, C APIs and documentation. If something needs to change, you change it in one place in the tool and all the subsequent files are regernerated correct by construction. With many designs having hundreds or thousands of registers to manage, this is a growing problem to be solved. Duolog has a few competitors as well, but their biggest competition is in-house home-grown scripts.
Of course, there were my 150 closest friends I know from years gone by, too numerous to mention, lest I leave someone out. I’m reminded of Sean Murphy’s perfect description of DAC:
An overall impression I, and many others, had was that the show floor was smaller and there were fewer attendees than in the past. The official preliminary numbers, however indicate that DAC was larger than last year, so I’m not sure whether to believe my eyes or the numbers.
For me personally, it was my annual chance to connect with the entire industry, so I got a lot out of it. At a minimum, it provided me with a lot of good ideas that I can work on for the next year.
harry the ASIC guy