harry … the ASIC guy

One of the shortest but most relevant exchanges during the Cadence analyst call concerning the Mentor acquisition was an exchange between Sterling Autry of JP Morgan and Kevin Palatnik, CFO of Cadence.

About 27 minutes into the conference call, Sterling Autry asked why Cadence was estimating only $50M in operating income benefit considering Mentor’s operating income in 2007 was $120M. Indeed, $1.6B to acquire $50M in income seems like a poor deal indeed.

Kevin Palatnik’s response included the following, “the industry has had a history, from a customer perspective, of trying to get more and include features and not pay for it. So I think we just have to be able to demonstrate value to the customers. So I think, in the short term, I think, there is always the customers asking for the combination and not paying for it.”

The crux of the issue is simple math: 1 + 1 = ??? …how much will Cadence-Mentor be able to charge for their combined products?  If  1+1 > 1.5, then the combined company will be in pretty good shape.  If 1 + 1 < 1.5, then it will be difficult to “extract the value” of the acquisition. In that case, expect lots of layoffs, products being scrapped, and products being sold off.

From my experience, Kevin Palatnik is only partially correct that “the industry has had a history, from a customer perspective, of trying to get more and include features and not pay for it”. When I started with Synopsys in 1992, their flagship tool was Design Compiler. Synopsys added new features and voila…DC-Expert.  Then DC-Ultra. Now DC-Graphical. Each one sold at a premium to the predecessor and customers would pay for the upgrades.

But not without voicing their displeasure, both privately and also publicly on places like ESNUG. It often seemed arbitrary and self-serving to customers what Synopsys deemed an “update” (covered by their tool support) and what they deemed an “upgrade”.  And they felt they were being nickel-and-dimed.

On the other hand, people need to eat, and the EDA tool developers are no exception. They do not work for free. It seems unique to the EDA industry, that customers expect, once they buy a tool, to get any and all improvements to the product for free. This is not the case when I buy MS Office or most any other desktop application, but it is definitely a reality in EDA.

To add to the confusion, I can now download almost any desktop application I need for free as open-source (e.g. Open Office), or use it for free online (e.g. Google Docs), and get access to upgrades for free as well. This has changed customer expectations dramatically.

I’d like to know what you (EDA vendors and customers) think about this:

1. Should customers pay more for EDA tool enhancements or should they be part of the tool “support”?
2. How do you decide what is an “update” and what is an “upgrade”?

harry the ASIC guy

“Never miss an opportunity to keep your mouth shut”.

I googled this quote and it looks like it might have been Mark Twain or Abraham Lincoln or someone around those times. Whoever it was, I took their advice last week regarding the Cadence - Mentor acquisition, at least as far as anything on this blog was concerned. I have my views as to what will likely happen, but I’ve expressed them privately for the most part. Instead, I was listening to what others had to say.

And boy are there lots of opinions! As the dust settles, I’ve noticed something very interesting. There seems to be two camps.

In one camp are the people who are opposed to the merger or feel it won’t work. I must admit that this is the camp I am in, informed by 14 years in the EDA industry and bystander to several mergers, good and bad. The specific reasons have already been covered by others. They raise the spectre of Daisy/Cadnetix, pointing out significant product overlap, the difference of corporate cultures, FTC concerns, etc.

In the other camp are those who think this is a good idea, good for the industry, good for the companies, good for the shareholders. And they are mainly from the financial analyst and investment community. I admit, I have only a rudimentary understanding of the Wall Street side of the business, and the finances involved, so I ask you for your help to explain to me…

What do the Analysts Know that We Don’t Know?

harry the ASIC guy

Several weeks ago, Tommy Kelly published a blog post entitled DAC and the VLSI Homunculus :

“To the unwary conference goer (and the EDA companies: my addition), the most important part of the VLSI design and verification problem, is tools. Choose the right tool, and you’ll be fine. Get it wrong, and you’ll never tape out a chip again…But far, far more important are the knowledge, skills, experience, and artistry of the people who use those tools. Peopleware, not Software or Hardware, is the most important VLSI body part.”

Having spent the last decade plus of my life in some way, shape, or form in the ASIC design consulting business, I could not agree with Tommy more. Never did my clients insist on using a particular tool. But almost always they’d ask for a consultant by name, because he had the “knowledge, skills, experience, and artistry” to get the job done.

And so, when I read the EE Times Story entitled EDA Vendors Get Squeezed on Two Fronts, I had to laugh. Here were the EDA vendors once again bemoaning the fact that the EDA industry is not able to “capture the value” (i.e. charge more for its products) that it justly deserves. The article referenced strategies such as royalties that have been rejected before. (After all, if you were a general contractor, would you pay a royalty to the company that made the hammer or the saw?)

Indeed, the EDA industry is largely a Cortical Homunculus, having a distorted view of how important it is to the success of it’s customers projects. Yes, the tools are a key enabler, but more important are the designers, the people using the tools. Through my years, I have had the honor or working with designers that I would take with me wherever I go, my A-Team. And it would not matter what tools they use, they’d be successful anyway they’d need to do it!!!

I’ve spent a good portion of the last year talking to people in the EDA industry, marketing people and sales people. They tell me things like the following:

• EDA is a dying business
• EDA companies are just trying to take market share from competitors
• There’s very little new in EDA
• All the innovation comes from the small companies

They are probably not listening to me, but just in case, here is my advice to the big EDA companies.

Try Something New!!!

Instead of stealing EDA share from eachother in the analog design or verification market, solve a new problem. Make our lives easier. In basic economic terms, there is only one type of company that “captures the value” of its offering, and that is the monopoly, the one-of-a-kind product that solves a must-solve problem.

harry the ASIC guy

(Postscript: I wrote this article prior to Cadence’s offer today to buy Mentor Graphics, but it relates to the same point. Instead of doing something new, the EDA vendor strategy is to take away, or in this case BUY, market share from its competitors.

This evening was the first Blogging Birds of a feather session at DAC. It was a very interesting session, mostly involving discussions between the “real journalists” in the room and the other bloggers. John Ford has already posted a very good summary of the meeting on DFT Digest, so please click over there to find out more. I’m also interested to see what the “real press” has to say.

harry the ASIC guy

I had successfully avoided the zoo that is Monday at DAC and spent Tuesday zig-zagging the exhibit halls looking for my target list of companies to visit. (And former EDA colleagues, now another year older, greyer, and heavier). Interestingly enough, the first and last booths I visited on Tuesday seemed to offer opposite approaches to address the same issue. It was the best of times, it was the worst of times.

A well polished street magician got my attention at first at the Certess booth. After a few card tricks, finding the card I had picked out in the deck, he told me that it was as easy for him to find the card as it was for Certess to find the bugs in my design. Very clever!!! Someone must have been pretty proud they came up with that one. In any case, I’d had some exposure to Certess previously and was interested enough to invest 15 minutes.

Certess’ tool does something they call functional qualification. It’s kinda like ATPG fault grading for your verification suite. Basically, it seeds your DUT with potential bugs, then considers a bug “qualified” if the verification suite would cause the bug to be controlled and observed by a checker or assertion. If you have unqualified bugs (i.e. aspects of your design that are not tested), then there are holes in your verification suite.

This is a potentially useful tool since it helps you understand where the holes are in your verification suite. What next? Write more tests and run more vectors to get to those unqualified bugs. Ugh….more tests? I was hoping this would reduce the work, not increase it!!! This might be increasing my confidence, but life was so much simpler when I could delude myself that my test suite was actually complete.

Whereas the magician caught my attention at the Certess booth, I almost missed the Nusym booth as it was tucked away in the back corner of the Exhibit Hall. Actually, they did not really have a booth, just a few demo suites with a Nusymian guarding the entrance armed with nothing more than a RFID reader and a box of Twinkies. (I did not have my camera, so you’ll have to use your imagination). After all the attention they had gotten at DVCon and from Cooley, I was surprised that “harry the ASIC guy” could just walk up and get a demo in the suite.

(Disclaimer: There was no NDA required and I asked if this was OK to blog about and was told “Yup”, so here goes…)

The cool technology behind Nusym is the ability to do on-the-fly (during simulation) coverage analysis and reactively focused vector generation. Imagine a standard System Verilog testbench with constrained random generators and checkers and coverage groups defining your functional coverage goal. Using standard constrained random testing, the generators create patterns independent of what is inside the DUT and what is happening with the coverage monitors. If you hit actual coverage monitors or not, it doesn’t matter. The generators will do what they will do, perhaps hitting the same coverage monitors over and over and missing others altogether. Result: Lots of vectors run, insufficient functional coverage, more tests needed (random or directed).

The Nusym tool (no name yet) understands the DUT and does on-the-fly coverage analysis. It builds an internal model that includes all of the branches in your DUT and all of your coverage monitors. The constraint solver then generates patterns that try to get to the coverage monitors intentionally. In this way, it can get to deeply nested and hard to reach coverage points in a few vectors whereas constrained random may take a long time or never get there. Also, when you trigger a coverage monitor, it crosses it off the list and know it does not have to hit that monitor again. So the next vectors will try to hit something new. As compared to Certess, this is actually reducing the number of tests I need to write. In fact, they recommend just having a very simple generator that defines the basic constraints and focusing most of the energy on writing the coverage monitors. Result: Much fewer vectors run, high functional coverage. No more tests needed.

It sounds too good to be true, but it was obvious that these guys really believe in this tool and that they have something special. They are taking it slow. Nusym does not have a released product yet, but they have core technology with which they are working with a few customers/partners. They are also focusing on the core of the market, Verilog DUT, System Verilog Testbench. I would not throw out my current simulator just yet, but this seems like very unique and very powerful technology that can get coverage closure orders of magnitude faster than current solutions.

If anyone else saw their demo or has any comments, please chime in.

harry the ASIC guy

Towards the end of my last post I mentioned a new company called Xuropa that is offering a Web 2.0 style Online Tradeshow Platform. As it turns out, Lou Covey covered them in his State of the Media blog today and also interviewed Xuropa founder James Colgan. Check it out.

FYI … You should also be able to meet James Colgan at the Bloggers Birds-of-a-Feather session at DAC.

Every year on March 19th, the swallows wing their way back to San Juan Capistrano. Just up the road in Anaheim, designers from around the world will fly in for the 45th Annual Design Automation Conference, held June 8th - 13th. How appropriate will it be then, when EDA and ASIC design bloggers flock to the 1st annual DAC Birds-of-a-Feather session on blogging?

Perhaps you are a blogger or are thinking of becoming a blogger or know somebody who is a blogger. Perhaps you are a marketing director or just curious. Whatever your interest, you’ll want to come meet and engage with the bloggers who are growing in quantity, quality and industry influence:

• Quantity: A quick check of the DAC home page shows 17 industry blogs, and there are at least a dozen more, including yours truly.
• Quality: Topics as diverse as verification, design for test, analog design, semiconductors, memory, good design techniques, and standards, are discussed by design experts who actually use the tools and do the work.
• Influence: These blogs have influenced standardization efforts and challenged the status quo.

This event will be held in Rooms 201B and 201C at the Anaheim convention center on Wednesday, June 11 at 6pm.

I am helping to coordinate this session, so if you are planning to attend, just drop a quick email to harry {at} theASICguy {dot} com so we can get an idea for how large a group we will have. If you are a blogger and would like to present or be part of a panel, please let me know as well.

I hope to see and meet many of you there.

harry the ASIC guy

OK … I’m registered to go to DAC for at least one day, maybe two. I’ll definitely be there on Tuesday and probably Wednesday evening for a Blogging “Birds-of-a-Feather” session that JL Gray is setting up. Besides hitting the forums and other activities, I’ll have about half a day to attack the exhibit floor or the “suites” to look at some new technology. If you want to meet up, drop me an email and we can arrange something.

Cadence won’t be there and I already talk to Synopsys and Mentor on a regular basis, so I’m planning on focusing on smaller companies with new technology. Here’s what’s on my list so far…

Nusym - They have some new “Path Tracing” technology that finds correlations between a constrained random testbench and hard-to-hit functional coverage points. With this knowledge, they claim to be able to modify the constraints to guide the simulation to hit the coverage points. The main benefit is in getting that last few % of functional coverage that can be difficult with unguided constrained random patterns.

Chip Estimate - Having been around for a few years and recently bought by Cadence, they are basically a portal where you can access 3rd party IP and use the information to do a rough chip floorplan. This allows you to estimate area, power, yield, etc. I’m real curious as to their business model and why Cadence bought them. At a minimum, it should be entertaining to see the hyper-competitive IP vendors present back-to-back at half hour intervals on the DAC floor.

I have a few others on my list, but there are so many small companies that it’s hard to go thru them all and decide what to see. That’s where I need your help.

What would you recommend seeing and why?

As I’ve been thinking a lot about Intellectual Property (IP) lately, I recently recalled a consulting project that I had led several years ago … I think it was 2002. The client was designing a processor chip that had a PowerPC core and several peripherals. The core and some of the peripherals were purchased IP and our job was to help with the verification and synthesis of the chip.

Shaun was responsible for the verification. As he started to verify one of the interfaces, he started to uncover bugs in the associated peripheral, which was purchased IP. We contacted the IP provider and were told most assuredly that it had all been 100% verified and silicon proven. But we kept finding bugs. Eventually, faced with undeniable proof of the poor quality of their IP, they finally fessed up. It seems the designer responsible for verifying the design had left the company half way through the project. They never finished the verification. Ugh 1!

Meanwhile, Suzanne was helping with synthesis of the chip, including the PowerPC core. No matter what she did, she kept finding timing issues in the core. Eventually, she dug into the PowerPC core enough to figure out what was going on. Latches! They had used latches in order to meet timing. All well and good, but the timing constraints supplied with the design did not reflect any of that. Ugh 2!

About a week later, I was called to a meeting with Gus, who was the client’s project lead’s boss’s boss. As I walked into his office, he said something that I’ll never forget …

“I’m beginning to believe that IP is a 4-letter word”.

How true. Almost every IP I have every encountered, be it a complex mixed-signal hard IP block, a synthesizable processor core, an IO library … they all have issues. How can an industry survive when the majority of the products don’t work? Do you think the HDTV market would be around if more than half the TVs did not work? Or any market. Yet this is tolerated for IP.

That is not to say that some IP providers don’t take quality seriously. Synopsys learned it’s lesson many years ago when it came out with a PCI core that was a quality disaster. To their credit, they took failure as a learning opportunity, developed a robust reuse methodology along with Mentor Graphics, and reintroduced a PCI core that is still in use today.

Still … no IP is 100% perfect out-of-the-box. IP providers need to have a relationship and business model with their customers that encourages open sharing of design flaws. This is a two-way street. The IP provider must notify its customers when it finds bugs, and the customer must inform the IP provider when it finds bugs. As an example, Synopsys and many other reputable IP providers will inform customers of any design issue immediately, a transparency that I could have only prayed for from the company providing IP to my client. In return, they need their customers support by reporting design issues to them. Sounds simple, right?

Maybe not. I had another client who discovered during verification that there was a bug in a USB Host Controller IP. They had debugged and corrected the problem already, so I asked the project manager if they had informed the IP provider yet. He refused. The rationale? He wanted his competition to have the buggy design while he had the only fix!

We, as users, play a role because we have a responsibility to report bugs for the good of all of us using the product. Karen Bartleson talks about a similar situation with her luggage provider, where customers are encouraged to send back their broken luggage in order to help the company improve their luggage design. The luggage gets better and better as a result.

So, besides reporting bugs and choosing IP carefully, what else can we as designers do to drive IP quality. I have one idea. One day, when I have some free time, I’d like to start an independent organization that would objectively assess and grade IP. We’d take it though all the tools and flows and look at all the views, logical and physical, and come out with an assessment. This type of open grading system would encourage vendors to improve their IP and would allow us to make more informed choices rather than playing Russian Roulette.

I’m half inclined to start one today … anybody with me?

harry the ASIC guy

On her Standards Game Blog  today, Karen Bartleson announced that Accellera is forming a subcommittee to define a standard for verification interoperability.  That is, to try to settle the VMM / OVM war.  As I have stated before in comments on JL Gray’s Cool Veification Blog, this is the right move because it give us input into the process, rather than just the EDA vendors controlling the process for their own benefit.  Also, as I argued in a previous post entitled “The Revolution Will Not Be Televised”, the influence and pressure of the verification community and especially the Cool Verification Blog were at least in part responsible.

Of course, Synopsys will tell you that they are just doing the right thing

It’s not clear how Cadence and Mentor will respond.  Hopefully they’ll join the effort.  Let’s keep the pressure on.