Archive for the ‘EDA’ Category

Brian Bailey on Unconventional Blogging

Tuesday, June 15th, 2010

bailey.jpg

(Photo courtesy Ron Ploof

I had the pleasure yesterday of interviewing Brian Bailey in the Synopsys Conversation Central Stage at DAC. We discussed his roots in verification working with the initial developers of digital simulation tools and his blogging experiences these past few years. There are, of course, even a few comments on the difference between journalists and bloggers ;)

You can listen to this half hour interview at the Synopsys Blog Talk Radio site. I’d be interested in your comments on the show and the format as well. It was pretty fun, especially in front of a live audience.

At 12:30 PDT today, I’ll be doing another interview on Security Standards for the Cloud. You can tune in live on your computer or mobile device by going to the main Synopsys Blog Talk Radio Page. So, even if you’re not here at DAC, you can still partake.

harry the ASIC guy

Where in the DAC is harry the ASIC guy?

Friday, June 11th, 2010

dac_logo.pngLast year’s Design Automation Conference was kind of quiet and dull, muted by the impact of the global recession with low attendance and just not a lot of real interesting new developments. This year looks very different; I’m actually having to make some tough choices of what sessions to attend. And with all the recent acquisitions by Cadence and Synopsys, the landscape is changing all around, which will make for some interesting discussion.

I’ll be at the conference Monday through Wednesday. As a rule, I try to keep half of my schedule open for meeting up with friends and colleagues and for the unexpected. So if you want to chat, hopefully we can find some time. Here are the public events that I have lined up:

Monday

10:30 - 11:00 My good friend Ron Ploof will interviewing Peggy Aycinena on the Synopsys Conversation Central stage, so I can’t miss that. They both ask tough questions so that one may get chippy. (Or you can participate remotely live here)

11:30 - 12:00 I’ll be on that same Synopsys Conversation Central stage interviewing Verification Consultant and Blogger Extraordinaire Brian Bailey. Audience questions are encouraged, so please come and participate. (Or you can participate remotely live here)

3:00 - 4:00 I’ll be at the Atrenta 3D Blogfest at their booth. It should be an interesting interactive discussion and a good chance to learn about one of the 3 directions EDA is moving in.

6:00 - Cadence is having a Beer for Bloggers event but I’m not sure where. For the record, beer does not necessarily mean I’ll write good things. (This event was canceled since there is the Denali party that night).

Tuesday

8:30 - 10:15 For the 2nd straight year, a large fab, Global Foundries (last year it was TSMC) will be presenting their ideas on how the semiconductor design ecosystem should change From Contract to Collaboration: Delivering a New Approach to Foundry

10:30 - 12:00 I’ll be at a panel discussion on EDA Challenges and Options: Investing for the Future. Wally Rhines is the lead panelist so it should be interesting as well.

12:30 - 1:00 I’ll be back at the Synopsys Conversation Central stage interviewing James Wendorf (IEEE) and Jeff Green (McAfee) about standards for cloud computing security, one of the hot topics.

Wednesday

10:30 - 11:30 I’ll be at the Starbucks outside the convention floor with Xuropa and Sigasi. We’ll be giving out Belgian Chocolate and invitations to use the Sigasi-Xilinx lab on Xuropa.

2:00 - 4:00 James Colgan, CEO of Xuropa, and representatives from Amazon, Synopsys, Cadence, Berkeley and Altera will be on a panel discussion on Does IC Design have a Future In the Cloud?. You know what I think!

This is my plan. Things might change. I hope I run into some of you there.

harry the ASIC guy

Oasys for FPGA Synthesis? Hmmmm….

Wednesday, June 9th, 2010

A friend asked me what I thought about Oasys’ announcement last week that Juniper Networks was now a customer of theirs. I’ll admit that I was lukewarm. On the one hand, a large high-end networking chip is exactly the sweet spot for a fast synthesis tool. On the other hand, it did not change the fact that the number of these large designs is dwindling and that the industry is looking more towards the front-end of the design cycle than the back.

So, today he asked me what I thought about Oasys’ announcement of it’s partnership with Xilinx. Now this was interesting. Here is what I wrote back:

__________

I’m not surprised. I had heard from some people that they had funding from Xilinx all along. Of course, they don’t say that in the press release :)

Truthfully, I think the FPGA market may be a better play than ASIC for a few reasons:

  1. FPGA design starts are growing while ASIC starts are shrinking
  2. Do not have to compete with Synopsys and Cadence for market share. These would be bloody battles requiring a lot of resources that Oasys does not have. Synopsys would win by attrition.
  3. FPGA synthesis is truly a bottleneck for FPGA designs. The debug loop for most people is design => synthesize/place&R => debug => fix error => synthesis/P&R….. It’s not uncommon for there to be dozens of these loops to get an FPGA working. And synthesis on a large FPGA can be an overnight run. If they can turn that into a half hour, then that changes the whole method of debug and can save weeks of schedule.

On the down side, ASPs for FPGA synthesis tools are $0 since Xilinx and Altera give theirs away for free, although Synopsys (Synplicity) and Mentor sell FPGA synthesis tools. This was discussed very recently on Olivier Coudert’s blog.

Will be interesting to watch.

__________

What do you think?

harry the ASIC guy

P.S. Oasys, can you get some real blogging software on your blog so people can leave their comments and thoughts there on your site and not on my blog. I don’t mind the traffic, but you are missing out on building a sizable following. Just some friendly advice.

DAC Yesterday, Today, and Tomorrow

Friday, May 28th, 2010

About a week ago, I got an email from someone I know doing a story on how the Design Automation Conference has changed with respect to bloggers since the first EDA Bloggers Birds-of-a-Feather Session 2 years ago. I gave a thoughtful response and some of it ended up in the story, but I thought it would be nice to share my original full response with you.

Has your perception of the differences between bloggers and press changed since the first BOF?

Forget my perception; many of the press are now bloggers! I don’t mean that in a mean way and I understand that people losing their jobs is never a good thing. But I think the lines have blurred because we all find ourselves in similar positions now. It’s not just in EDA … many, if not most, journalists also have a blog that they write on the side.

Ultimately, I think either the traditional “press” or a blog is just a channel between someone with knowledge to people who want information they can trust. What determines trust is the reliability of the source. In thepast, the trust was endowed by the reputation of the publication. Now, weall have to earn that trust.

As for traditional investigative journalism (ala All the President’s Men) and reporting the facts (5 Ws), I think there is still a role for that, butmost readers are looking for insight, not jut the facts.

What do you think of DAC’s latest attempts to address these differences, e.g. Blog-sphere on the show floor, press room in the usual location?

Frankly, I’m not sure exactly what DAC is doing along these lines this year. Last year bloggers had very similar access as journalists to the press room and other facilities. It was nice to be able to find a quiet place to sit, but since most bloggers are not under deadline to file stories it is not as critical. Wireless technology is making a lot of this obsolete since we can pretty much work from anywhere. Still, having the snacks is nice :)

What does the future hold for blogging at DAC?

Two years ago, blogging was the “new thing” at DAC. Last year, blogging was mainstream and Twitter was the new thing. This year blogging will probably be old skool and there will be another “new thing”. For instance, I think we’re all aware and even involved in Synopsys’ radio show. This stuff moves so fast. So, I think the future at DAC is not so much for blogging, as it is for multiple channels of all kinds, controlled not only by “the media”, but also the vendors, independents, etc. Someone attending DAC will be able to use his wireless device to tap into many channels, some in real-time.

Next year, I predict that personalized and location aware services will be a bigger deal. When you come near a booth, you may get an invitation for a free demo or latte if your profile indicates you are a prospective customer. You’ll be able to hold up your device and see a “google goggles” like view of the show floor. You may even be able to tell who among your contacts is at the show and where they are. Who knows? It will be interesting.

harry the ASIC guy

Which Direction for EDA - 2D, 3D, or 360?

Sunday, May 23rd, 2010

2d3d360.JPGA hiker comes to a fork in the road and doesn’t know which way to go to reach his destination. Two men are at the fork, one of whom always tells the truth while the other always lies. The hiker doesn’t know which is which. He may ask one of the men only one question to find his way.

Which man does he ask, and what is the question?

__________

There’s been lots of discussion over the last month or 2 about the direction of EDA going forward. And I mean literally, the “direction” of EDA. Many semiconductor industry folks and proponents have been telling us to hold off on that obituary for 2D scaling and Moore’s law. Others have been doing quiet innovation in the technologies needed for 3D die and wafer stacks. And Cadence has recently unveiled its holistic 360 degree vision for EDA that has us developing apps first and silicon last.

I’ll examine each of these orthogonal directions in the next few posts. In this post, I’ll first examine the problem that is forcing us to make these choices.

The Problem

One of the great things about writing this blog is that I know that you all are very knowledgeable about the industry and technology and I don’t need to start with the basics. So I’ll just summarize them here for clarity:

  • Smaller semiconductor process geometries are getting more and more difficult to achieve and are challenging the semiconductor manufacturing equipment, the EDA tools, and even the physics. No doubt there have been and always will be innovations and breakthroughs that will move us forward, but we can no longer see clearly the path to the next 3 or 4 process geometries down the road. Even if you are one of the people who feels there is no end to the road, you’d have to admit that it certainly is getting steeper.
  • The costs to create fabs for these process nodes is increasing drastically, forcing consolidation in the semiconductor manufacturing industry. Some predict there will only be 3 or 4 fabs in a few years. This cost is passed on to the cost of the semiconductor device. Net cost per gate may not be rising, but the cost to ante up with a set of masks at a new node certainly is.
  • From a device physics and circuit design perspective, we are hitting a knee in the curve where lower geometries are not able to deliver on the full speed increases and power reductions achieved at larger nodes without new “tricks” being employed.
  • Despite these challenges, ICs are still growing in complexity and so are the development costs, some say as high as $100M. Many of these ICs are complex SoCs with analog and digital content, multiple processor cores, and several 3rd party IP blocks. Designing analog and digital circuits in the same process technology is not easy. The presence of embedded processors means that software and hardware have intersected and need to be developed harmoniously … no more throwing the hardware over-the-wall to software. And all this 3rd party IP means that our success is increasingly dependent on the quality of work of others that we have never met.
  • FPGAs are eating away at ASIC market share because of all the factors above. The break even quantity between ASIC and FPGA is increasing, which means more of the lower volume applications will choose FPGAs. Nonetheless, these FPGAs are still complex SoCs requiring similar verification methods as ASICs, including concurrent hardware and software development.

There are no doubt many other factors, but these are the critical ones in my mind. So, then, what does all this mean for semiconductor design and EDA?

At the risk of using a metaphor, many feel we are at a “fork-in-the-road”. One path leads straight ahead, continuing the 2D scaling with new process and circuit innovations. Another path leads straight up, moving Moore’s law into the 3D dimension with die stacks in order to cost effectively manage increasing complexity. And one path turns us 180 degrees around, asking us to look at the applications and software stack first and the semiconductor last. Certainly, 3 separate directions.

Which is the best path? Is there another path to move in? Perhaps a combination of these paths?

I’ll try to examine these questions in the next few posts. Next Post: Is 2D Scaling Really Dead or Just Mostly Dead?

__________

Answer to Riddle: Either man should be asked the following question: “If I were to ask you if this is the way I should go, would you say yes?” While asking the question, the hiker should be pointing at either of the directions going from the fork.

harry the ASIC guy

Monterey Pop and Mookie

Thursday, April 15th, 2010

MookieLast week I wrote that the EDP Symposium in Monterey was going to be interesting on four different accounts. I was more right than I could have known.

First, it certainly proved to be unique. Having coffee before the first session on Wednesday morning, I got to meet Tom Williams of Synopsys, which was a real treat for me. You see, my first job out of college back in 1985 was to design a BIST system for a wafer-scale chip. Back then, there really were not any automated DFT or BIST tools, so I spent a lot of time reading IEEE papers and other publications written by Tom Williams (one of the inventors of LSSD at IBM) and other pioneers of DFT like Johnny LeBlanc (a buddy of Tom’s I found out). We shot the bull like old friends and reminisced about the early days of DFT

As it turned out, Dr. Williams gave the first presentation, which was sort of a keynote for the Symposium. Entitled “An Inconvenient Truth”, patterned after Al Gore’s Oscar winning documentary of the same name, Dr. Williams put forth some very convincing arguments that the end of scaling is very close at hand. The first reason is that leakage current increases ~10x for each 70 mv in Vt reduction. Even today, reductions in device size yield little to no power benefit. Combine that with the cost of moving to a new node and you can see that advances in process node will certainly slow down. The solution? Go 3-D. System-in-package techniques will be the next logic step to increasing density and lowering power, including optical interconnects. OK, nothing we haven’t heard before, but considering the source, it’s something to be aware of.

At lunch, David Stanasolovich, a GM at Intel, described some of the challenges in managing a data-center comprised of 70,000 servers. It was interesting to hear how they try to maintain > 80% CPU utilization while providing reasonable job queue wait times within a fixed budget. Intel uses > 100 tools in its design flow and completes almost 20 million compute jobs per week. Wow!

The early afternoon was dedicated to discussions of high performance computing and multi-core for EDA. Richard Goering had a very good writeup on these sessions, so check that out for more details. Let’s just say that there were some differences of opinion. In the end, I think the jury is still out as to whether EDA tools can really take full advantage of large scale multi-core parallelism.

Dinner was out on a restaurant on Monterey Bay and included a presentation by Andreas Kuehlmann who leads Cadence Berkeley labs. Rather than a dry, boring presentation, he looked at the wackier side of EDA and EDA benchmarks as well as the early pioneers of EDA. I’m still trying to figure out who was in the hot tub photo circa 1980.

Second, this definitely was a conference for EDA people and not for shmoozing customers. The coffee was bad and the continental breakfast provided calories and not much more. The room was small and the sound system didn’t work. Instead of freebie handouts such as backpacks we got a tiny pad of paper and a hotel pen to take notes. Don’t get me wrong … I’m not complaining. Indeed, it was exactly the kind of meeting I expected where content was more important than appearances. And if a customer came to hear some marketing pitch for a tool, he would have been shocked to hear developers openly discuss buggy software and even share ideas between competitors.

Third, moderating my sessions was much less of a big deal than I thought. The session, entitled “Moving to a Brave New World” included presentations from James Colgan of Xuropa, Cliff Sze of IBM, and Shameen Akhter of Intel. James of Xuropa described how Cloud Computing is being used for EDA and Intel seemed to take notice. Cliff described how IBM has held contests to develop new EDA algorithms and how they got such good results that they actually incorporated the new algorithms into their production tools. And Shameen described how research into the biology of the brain can be used to understand multi-processing systems better.

Fourth, my family did not end up coming on the trip after all. You see, my wife had a bad cold, so we decided it was best that she and the kids stay home rather than take a vacation while sick. I was very disappointed, but as it turns out, it was a blessing in disguise. The day I left, our dog Mookie became very ill all of a sudden and needed an emergency surgery to save his life. Had he been in the kennel, he might not be with us anymore. And that would have been very sad.

Indeed, an interesting few days that I will never forget.

harry the ASIC guy

Small Gathering in Monterey

Sunday, April 4th, 2010

There’s going to be a small gathering of luminaries in Monterey this week. And no, it’s not the jellyfish at the Monterey Bay Aquarium.

Jellyfish at Monterey Bay Aquarium

http://www.flickr.com/photos/warthog9/ / CC BY-NC-SA 2.0

It’s the Electronic Design Processes Symposium Workshop. This will be my first time attending and it will be very interesting on several accounts.

First, everyone who has attended in the past has said that it’s truly unique in the industry. It’s not really a conference but a workshop, a small gathering of the best and brightest in EDA exchanging their research and ideas. With only 25-50 participants, it’s not uncommon for someone to  stand up and challenge the presenter or for spontaneous discussions to break out during sessions. It’s not uncommon to meet people who have been thinking about the same problems you’ve considered or someone who has been thinking about problems you never thought existed. And it’s not uncommon to walk away with new insights and revelations and ideas.

Second, there probably are very few, if any, EDA customers attending. This is an EDA workshop for EDA people. There is no trade show. There are no booths to set up. There are no big press releases or sales guys walking up to shake your hand or schlocky giveaways. I imagine that DAC probably started out this way back in the 1960s, but DAC is now more of a trade show that a workshop. This will be back to the grass roots of EDA.

Third, I am going to be moderating one of the sessions, something I’ve not done before (except at my own round table). I’ll be moderating the session entitled “Moving to a Brave New World” which includes a presentation by James Colgan of Xuropa on cloud computing. Obviously, I’m a little biased on that topic, but I’ll try not to let that influence my moderation. I’m sure this and all the other sessions will be very interesting.

Last, I’m going to be traveling with my family. It’s spring break week and so we’re heading up the coast to visit Monterey for a few days, then visit some friends up in Danville. Fortunately there is plenty to do in Monterey and the hotel is right on the beach, so they’ll be fine. So, if you want to meet me or my family, come on over. Registration is still open.

We promise we won’t sting.

harry the ASIC guy

Why?

Monday, March 15th, 2010

Simon Sinek Golden CircleThe other day, I was listening to John Wall interview Simon Sinek on the Marketing over Coffee Podcast. Simon Sinek is a marketing consultant and motivational speaker and has a book out entitled “Start with Why: How Great Leaders Inspire Everyone to Take Action.” In addition to the podcast interview, I also came across the following presentation that Simon gave at a TedX conference a few months ago.

To make a long-story short, the key premise is that companies spend too much time marketing what they do and how they do it better than the other guy. This strategy may win you customers in the short-term, but only until the next guy comes along with a better offering.

Instead, Sinek contends that companies need to inspire customers by talking about why their company exists and how they intend to change the world. All people, and this includes customers, want to be inspired and to follow leaders with vision that matches theirs. Companies that can inspire effectively will gain loyal customers that will continue to buy even when a competitor offers a superior product at a lower cost.

Dell and HP and Gateway are busy telling us what they do, that they make computers that are higher speed, lower power, lower weight, better graphics, and lower in price than the competitor. And they can certainly sell computers in that manner … until a competitor beats them on one or more of these metrics. These companies are closing transactions, not gaining customers.

In contrast, Apple tells its story something like this: “we exist to challenge the status quo by making products that are elegant and easy to use”. To Apple’s customers, it doesn’t matter that PCs are less expensive or have longer battery life or support more software. Or that other smart phones can run multiple applications or have an open source OS or support a carrier with better 3G coverage. Or that other tablet computers have a camera or 3G or a phone built in. Apple’s customers are inspired by Apple’s story and will buy whatever Apple sells. Some call them blindly loyal, but who wouldn’t want to have customers like that.

There are lots of other examples. Nike inspires us to “just do it”. Harley Davidson inspires the Hell’s Angel in each of us. The Chicago Cubs prove that you can have an inferior product for a long time and still have the most loyal customers. (For the record, not a strategy I recommend). The Oakland Raiders, on the other hand, prove that loyalty doesn’t have to have a positive message, just one that inspires us.

And it’s not just about the customers. Employees can be inspired as well. An uninspired employee will leave if the pay is better or the commute is shorter or the work is more interesting elsewhere. An inspired employee will enthusiastically work longer hours for a lower salary just to be part of something special. And he won’t leave.

I admit that this idea is not really new. Seth Godin contends that people want to join Tribes and be led by leaders with vision. It’s really the same thing, put a little differently.

This seems to make sense in the business-to-consumer (B2C) market, but what about business-to-business (B2B). Can businesses really be inspired? Would they ever ignore their tradeoff charts, evaluation criteria, benchmarks, and ROI calculations and just go with their “gut feel”?

What about EDA? Clearly, this is an industry where marketing has been all about features and benefits. Has there ever been an EDA company that really inspired customers?

I may be a bit biased, but I think Synopsys was one of those companies when it first started out. As a Synopsys customer, I was inspired by the gospel of high-level design. So much so, that I got myself a job at Synopsys as an AE evangelizing the good news. (That’s really what we called it … evangelizing). To be part of a movement that changed the world (at least the EDA world) was exciting. It helped that we were small and close to the founders who had the original vision for the company. After all, we could carefully hire only those who shared our vision and would faithfully represent us to our customers.

But what about EDA today? Are there companies that inspire you, that you’d buy from even if their product is not the best? Does loyalty exist today anymore?

And if you run an EDA company, does your company inspire? Do you tell people why you exist, or just what you do? If it’s the latter, it might make sense to try the former.

Why not?

harry the ASIC guy

The Burning Platform

Monday, March 1st, 2010

The Burning PlatformAlthough I was unable to attend DVCon last week, and I missed Jim Hogan and Paul McLellan presenting “So you want to start an EDA Company? Here’s how“, I was at least able to sit in on an interesting webinar offered by RTM Consulting entitled Achieving Breakthrough Customer Satisfaction through Project Excellence.

As you may recall, I wrote a previous blog post about a Consulting Soft Skills training curriculum developed by RTM in conjunction with Mentor Graphics for their consulting organization. Since that time, I’ve spoken on and off with RTM CEO Randy Mysliviec. During a recent conversation he made me aware of this webinar and offered one of the slots for me to attend. I figured it would be a good refresher, at a minimum, and if I came out of it with at least one new nugget or perspective, I was ahead of the game. So I accepted.

I decided to “live tweet” the seminar. That is to say, I posted tweets of anything interesting that I heard during the webinar, all using the hash tag #RTMConsulting. If you want to view the tweets from that webinar, go here.

After 15 years in the consulting biz, I certainly had learned a lot, and the webinar was indeed a good refresher on some of the basics of managing customer satisfaction. There was a lot of material for the 2 hours that we had, and there were no real breaks, so it was very dense and full of material. The only downside is that I wish there had been some more time for discussion or questions, but that’s really a minor nit to pick.

I did get a new insight out of the webinar, and so I guess I’m ahead of the game. I had never heard of the concept of the “burning platform” before, especially as applies to projects. The story goes that there was an oil rig in the North Sea that caught fire and was bound to be destroyed. One of the workers had to decide whether to stay on the rig or jump into the freezing waters. The fall might kill him and he’d face hypothermia within minutes if not rescued, but he decided to jump anyway, since probable death was better than certain death. According to the story, the man survived and was rescued. Happy ending.

The instructor observed that many projects are like burning platforms, destined for destruction unless radically rethought. In thinking back, I immediately thought of 2 projects I’d been involved with that turned out to be burning platforms.

The first was a situation where a design team was trying to reverse engineer an asynchronously designed processor in order to port it to another process. The motivation was that the processor (I think it was an ADSP 21 something or other) was being retired by the manufacturer and this company wanted to continue to use it nonetheless. We were called in when the project was already in trouble, significantly over budget and schedule and with no clear end in sight. After a few weeks of looking at the situation, we decided that there was no way they would ever be able to verify the timing and functionality of the ported design. We recommended that they kill this approach and start over with a standard processor core that could do the job. There was a lot of resistance, especially from the engineer whose idea it was to reverse engineer the existing processor. But, eventually the customer made the right choice and redesigned using an ARM core.

Another group at the same company also had a burning platform. They were on their 4th version of a particular chip and were still finding functional bugs. Each time they developed a test plan and executed it, there were still more bugs that they had missed. Clearly their verification methodology was outdated and insufficient, depending on directed tests and FPGA prototypes rather than more current measurable methods. We tried to convince them to use assertions, functional coverage, constrained random testing, etc. But they were convinced that they just had to fix the few known bugs and they’d be OK. From their perspective, it wasn’t worth all the time and effort to develop and execute a new plan. They never did take our recommendations and I lost track of that project. I wonder if they ever finished.

As I think about these 2 examples, I realize that “burning platform” projects have some characteristics in common. And they align with the 3 key elements of a project. To tell if you have a “burning platform” on your hands, you might ask yourself the following 3 questions:

  1. Scope - Are you spending more and more time every week managing issues and risks? Is the list growing, rather than shrinking?
  2. Schedule - Are you on a treadmill with regards to schedule? Do you update the schedule every month only to realize that the end date has moved out by a month, or more?
  3. Resources - Are the people that you respect the most trying to jump off of the project? Are people afraid to join you?

If you answered yes to at least 2 of these, then you probably have a burning platform project on your hands. It’s time to jump in the water. That is, it’s time to scrap the plan and rethink your project from a fresh perspective and come up with a new plan. Of course, this is not a very scientific way of identifying an untenable project, but I think it’s a good rule-of-thumb.

There are other insights that I had from the webinar, but I thought I’d only share just the one. I don’t know if this particular webinar was recorded, but there are 2 more upcoming that you can attend. If you do, please feel free to live tweet the event like I did, using the #RTMConsulting hash tag.

But please, no “flaming” :-)

harry the ASIC guy

So, you want to start an EDA company?

Tuesday, February 9th, 2010

www.flickr.com/photos/cayusa/ CC BY-NC 2.0Lightbulb

In the almost 2 years since I started this blog, I’ve been paying pretty close attention to the EDA industry. And one of the themes I keep hearing goes something like this:

“There’s no more innovation in EDA”
I hear it on blogs and on Twitter. I hear it from design engineers, from consultants, from old media, from new media, and even from EDA people.

One person I know, someone who has been an executive at an EDA company and a venture capitalist, says that EDA is persona non-grata for VC folks. Maybe you can start a “lifestyle company” doing EDA, but don’t expect any more companies like Synopsys to come along.

And then, about a month ago, I get an email from someone out of the blue. He’s got an idea for a new EDA tool that would transform the industry. He’s been in the semiconductor business. He’s developed EDA tools. He knows everybody there is to know. And he’s not able to get anyone’s attention. As he puts it, nobody is working on anything “disruptive”. They are all doing “incremental improvements” that are “woefully inadequate”.

I spent about an hour talking to him on the phone. As I got off the phone, I was not sure what to make of the conversation. He was either insane or a visionary. He was either deluded or optimistic. He was either obsessed or determined. I’m still not sure which.

And that is what makes this industry so much frickin’ fun! You never know. That crazy idea of turning VHDL into gate-level schematics … who figured that would be the biggest innovation in design in decades?

Then, last week, I heard about this event/gathering/workshop happening during DVCon at the San Jose Doubletree. Presented by EDA veterans Jim Hogan and Paul McLellan. It’s called “So, you want to start an EDA Company. Here’s how …” And I immediately thought of my new friend with the idea about a new EDA company. This is exactly what he was looking for … an audience of people with open minds who were asking “why not” instead of “why”.

Maybe you also have a crazy idea. Maybe it really is crazy. Or maybe not.

I invited him and I hope I can get there myself. If so, I think you might want to come too.  You might just meet the founder of the next Synopsys. Here’s the skinny: San Jose Doubletree on Feb 23 at 6:30-7:30 in the Oak Ballroom.

I’ve also written a little prediction of what I expect to hear on the Xuropa Blog. Who knows? Maybe the naysayers are right and EDA is Dead. Then again, maybe not. I, for one, am dying to find out which.

harry the ASIC guy