harry … the ASIC guy

I mentioned a few weeks ago that I am wrapping up a project with one of my clients and beating the bushes for another project to take its place. As part of my search, I visited a former colleague who works at a small company in Southern California. This company designs a variety of products that utilize FPGAs exclusively (no ASICs), so I got a chance to understand a little bit more about the differences between ASIC and FPGA design. Here’s the follow-on then to my previous post An ASIC Guy Visits An FPGA World.

Recall that the first 4 observations from my previous visit to FPGA World were:

Observation #1 - FPGA people put their pants on one leg at a time, just like me.

Observation #2 - I thought that behavioral synthesis had died, but apparently it was just hibernating.

Observation #3 - Physical design of FPGAs is getting like ASICs.

Observation #4 - Verification of FPGAs is getting like ASICs.

Now for the new observations:

Observation #5 - Parts are damn cheap - According to the CTO of this company, Altera Cyclone parts can cost as little as $10-$20 each in sufficient quantities. A product that requires thousands or even tens of thousands will still cost less than a 90nm mask set. For many non-consumer products with quantities in this range, FPGAs are compelling from a cost standpoint.

True, the high-end parts can cost thousands or even tens of thousands each (e.g. for the latest Xilinx Virtex 6). But considering that a Virtex 6 part is 45nm and has the gate-count equivalent of almost 10M logic gates, what would an equivalent ASIC cost?

Observation # 6 - FPGA verification is different (at least for small to medium sized FPGAs) - Since it is so easy and fast and inexpensive (compared to ASIC) to synthesize and place and route an FPGA, much more of the functional verification is done in the lab on real hardware. Simulation is typically used to get a “warm and fuzzy” that the design is mostly functional, and then the rest is done in the lab with the actual FPGA. Tools like Xilinx ChipScope allow logic-analyzer-like access into the device, providing some, but not all, of the visibility that exists in a simulation. And once bugs are found, they can be fixed with an RTL change and reprogramming the FPGA.

One unique aspect of FPGA verification is that it can be done in phases or “spirals”. Perhaps only some of the requirements for the FPGA are complete or only part of the RTL is available. No problem. One can implement just that part of the design that is complete (for instance just the dataplane processing) and program the part. Since the same part can be used over and over, the cost to do this is basically $0. Once the rest of the RTL is available, the part can be reprogrammed again.

Observation # 7 - FPGA design tools are all free or dirt cheap - I think everybody knows this fact already, but it really hit home talking to this company. Almost all the tools they use for design are free or very inexpensive, yet the tools are more than capable to “get the job done”. In fact, the company probably could not operate in the black if they had to make the kind of investment that ASIC design tools require.

Observation # 8 - Many tools and methods common in the ASIC world are still uncommon in this FPGA world - For this company, there is no such thing as logical equivalence checking. Verification tools that perform formal verification of designs (formal proof), System-Verilog simulation, OVM, VMM…not used at all. Perhaps they’ll be used for the larger designs, but right now they are getting along fine without them.

__________

FPGA verification is clearly the area that is the most controversial. In one camp are the “old skool” FPGA designers that want to get the part in the lab as soon as possible and eschew simulation. In the other camp are the high-level verification proponents who espouse the merits of coverage-driven and metric-driven verification and recommend achieving complete coverage in simulation. I think it would really be fun to host a panel discussion with representatives from both camps and have them debate these points. I think we’d learn a lot.

Hmmm…

harry the ASIC guy

A colleague of mine, Alvin Cheung, recently interviewed Chris Schalick of GateRocket regarding his experiences in founding a high-tech startup company. That interview is reposted below by permission of both parties.

__________

Chris Schalick is VP of Engineering, CTO, and Founder of GateRocket, Inc. After working in the ASIC and FPGA industry for more than 15 years, Chris founded the company to solve one of the fundamental problems with FPGA design, the ability to simulate hardware FPGA behavior within the design verification environment. GateRocket partners with the three major Electronic Design Automation (EDA) providers, Mentor Graphics, Cadence, and Synopsys, to be able to “plug-in” their hardware to the software simulation environment.

Alvin Cheung is currently a CAD Manager in the aerospace industry. Previously, Alvin worked at TI, Artisan Components and other companies doing ASIC and library development.

__________

Alvin: Hi Chris. I want to start off by asking a couple of questions that are not necessarily related to FPGA technology but more towards a start-up company. I see that you founded the company in Oct. 2004. You were working for someone else before you decided to found your company. What made you want to start you own business?

Chris: Well, it is something that I always wanted to do as a kid. I love to build things. In the 15 years that I was an ASIC designer, I saw that when I went from ASIC to FPGA there were a lot of problems with debugging the FPGA. The parts that would work in simulation perfectly ended up not working in the lab at all. A lot of ASIC designers have the same issues going from ASIC to FPGA and there were not any tools out there to address this problem. I thought to myself, “There has to be a better way to do the debugging on the FPGAs.” That’s how I came up with the idea. I tested the idea with a couple of colleagues and founded the company. Our RocketDrive builds on the idea of using a logic analyzer in the lab and puts it at the finger tips of the designers doing functional verification with a simulator. You don’t have to reprogram the FPGA over and over again, troubleshoot, and recode your design.

Alvin: Did you find that you needed to adapt from your engineering skills to marketing or sales skills? Did you find that a challenge and a difficult transition?

Chris: In a small company you have to do a lot of things. In the beginning, I had to do everything from calling the customers, talking to the vendors, talking to partners and talking to investors. You’re right in that most engineers don’t have a lot of skills in those areas. I had to learn a lot by trial and error.

Alvin: Do you see a change in lifestyle since you started the company? Is it worthwhile?

Chris: I worked at several start-ups before starting GateRocket. I’m used to working long hours and with a small group of people. Over time, working focused hours with a small group can be more productive than larger groups with more resources. Our company has had its up and downs; keeping a positive attitude and going back to do the right thing is the most important thing.

Alvin: I see that you’ve secured your funding from venture and angel investors. Was it difficult to secure the Series A funding? Did the VC require you to change your plans? Were there a lot of obstacles?

Chris: Raising money is trial and error. The process is always lengthy but not necessarily an obstacle. There are always people who will say “No” and want you to address “one more” thing, but addressing it does not necessary mean that they’ll invest or that you will succeed. All you really need is the one “Yes” from the right guys and you can’t be concerned about the “No’s”. As far as the obstacles, they always want more data, analysis, financial projections and references. Those things are not unreasonable and you do your best to provide them with the information. When I put my own money on the line, I ask for the same things.

Alvin: How long did it take you to develop the “RocketDrive? Is it your first product?

Chris: Yes, the “RocketDrive” is our first product and our only product. It took me 18 months for the first prototype and since our first prototype we have dramatically enhanced the hardware. It took us 2 ½ years to ship our 1st production unit and we worked closely with our customers and partners to develop the product. We are in our 5th year and shipping units. We are constantly improving the product and continue development of RocketDrive as a platform and new software products that run on it. Stay tuned!

Alvin: What would you say are the top three skills needed to be a successful entrepreneur?

Chris: Hmm… I would say the ability to maintain focus. Things don’t always go the way you want. Many things that you don’t expect to happen will happen. You have to maintain focus and go back and look at problems from another angle. The second would be the ability to stay positive. You just keep your chin up and tell yourself you can do it. The third would be imagination. Sometimes the right answer is not obvious. There’s a saying that, “You have to think outside the box.” You really do to succeed. You need to see things from many different angles and sometimes the right answer is not the obvious one. Our first prototype was nothing like what we currently ship.

Alvin: What is your favorite aspect of being an entrepreneur?

Chris: You know the saying that, “You have to play big to win big.”? Well that’s true. From the creative aspect, I’ve always liked to build things and starting a company provides a unique chance to build things that you might not otherwise be able to. Of course money is also a big factor. Although there’s no guarantee of financial success, it certainly is a motivator. I would say it is the combination of the two.

Alvin: Was there a lot of trial and error with your product? Do you find yourself in situations where there is already a competitor out there that has similar technology? If yes, how did you differentiate them from your product?

Chris: There was a huge amount of trial and error. Success is always a trial. Sometimes the answers are not obvious. You have to be persistent and look outside the box. You keep looking for the solution until your find the answers. Our current model looks nothing like our original prototype on the inside. On the outside with the simulator, it looks the same. But on the inside, everything has changed. We believe we are the first product in the market that does logic simulation directly with the FPGA. So, no, there is no direct competition. There are alternatives to develop FPGAs – build a prototype, program the FPGA, take it to the lab, connect it to the logic analyzer and hope everything works according to what you simulate with your RTL and testbench. What we are doing is changing the design flow and people’s concept of verifying the design. You can debug your design on actual silicon before you take it to the lab.

Alvin: How is your company adjusting to the current economic downturn? Did you have to downsize or change your priorities to adjust?

Chris: The environment looks bad on the surface, but people are still working on FPGAs. Some people have fewer dollars to spend, but we are still getting positive feedback with our product and we are selling more of them. We certainly have lots of activity lately with our product due to the growing size and number of FPGA designs.

Alvin: Actually in the current economic climate, would people choose FPGA over ASIC?

Chris: Yes, you are right. With the cost of the ASIC process, more and more people are looking to see how they can fit their designs in FPGAs instead of ASICs. With FPGAs getting larger and design technology getting smaller, more and more designers are choosing FPGA for their designs.

Alvin: I’m going to ask my last question of the interview and don’t want to take too much of your time. So I’m going to end with asking, what is your next step? Where do you see the company going from here?

Chris: Though our company is still growing, we are looking for ways to become the household name when it comes to FPGA development. We are demo’ing to customers and showing them the actual behavior of the simulator on silicon. We are working to craft the message and to expand our presence in the market. We are developing our online presence. We are going to DVCon, FPGA summit, and DAC, and really our best marketing is from “word of mouth”. We want our customers to be successful and in turn we can become successful.

Alvin: Do you think you would IPO or get the company to be on a merger/acquisition deal anytime soon?

Chris: In this environment, I don’t think it is the right time for an IPO. We are focusing on our customers, enhancing the product and expanding our market presence.

Alvin: Ok. Well, thank you for letting me take a big chunk of your time from your busy schedule. Thank you so much for the interview.

Last Wednesday at DVCon, Peggy Aycinena MC’ed what used to be known as the Troublemakers Panel, formerly MC’ed by John Cooley. The topic, “EDA: Dead or Alive?” Well, having attended Aart’s Keynote address immediately preceding and having attended Peggy’s panel discussion, I can answer that question in the immortal words of Miracle Max, “EDA is only MOSTLY dead”. But first, some background.

Back in the mid 90s, I attended a Synopsys field conference where Aart delivered a keynote addressing the challenges of achieving higher and higher productivity in the face of increasing chip size. The solution, he predicted, would be design reuse in the form of intellectual property. Although most of us had only the faintest idea of what design reuse entailed and could barely fathom such a future, Aart’s prediction has indeed come true. Today, there is hardly a chip designed without some form of soft or hard IP and many chips are predominantly IP.

Some years later, he delivered a similar keynote preaching the coming future of embedded software. This was before the term SoC was coined to designate a chip with embedded processors running embedded software. Again, only a handful understood or could fathom this future, but Aart was correct again.

So, this year, immediately preceding Peggy’s Panel, Aart delivered another very entertaining and predictive keynote. After describing the current economic crisis in engineering terms using amplifiers and feedback loops, he moved to the real meat of the presentation which addressed the growing amount of software content in today’s SoCs. He described how project schedules are often paced by embedded software development and validation. How products are increasingly differentiated based on software, not hardware. And he predicted a day when chips would only have custom hardware to implement functions that could not be performed with programmable software. In essence, he described a future with little electronic design as we know it today, where hardware designers are largely replaced by programmers.

Immediately following Aart’s keynote was Peggy’s panel. (If you want to know exactly what occurred, there is no place better to go than Mike Demler’s blow-by-blow account.) Peggy did her best to challenge the EDA execs to defend why EDA would not die out. She kept coming back to that same question in different ways and the execs kept avoiding directly answering the question, choosing instead to offer such philosophical logic such as: “If EDA is dead, then semiconductors are dead. If semiconductors are dead, then electronics are dead. And since electronics will never die, EDA will never die”.

On the surface, logic such as this is certainly comforting. After all, who can imagine a future without electronics? Upon closer inspection, however, and in light of Aart’s keynote, there is plenty reason for skepticism.

Just as Aart was right about design reuse and IP…

Just as Aart was right about embedded software …

I believe that Aart is right about hardware design being replaced by software development.

As processors and co-processors become faster and more capable of handling tasks formerly delegated to hardware…

As time-to-market drives companies to sell products that can be upgraded or fixed later via software patches…

As fewer and fewer companies can afford the cost of chip design at 32nm and below…

More companies will move capabilities to software running on standard chips.

With that, what becomes of the current EDA industry. Will it adapt to embrace software as part of its charter. Or will it continue to focus on chip development.

Personally, I think Aart is right again. Hardware will increasingly become software. And an EDA industry focused on hardware, will be increasingly “mostly dead”.

harry the ASIC guy

I’m still up at the Design Verification Conference (DVCon) and have not had a chance to summarize last evening’s Software-As-A-Service and Cloud Computing EDA Roundtable. I will do that over the weekend and have a complete rundown next week, including slides.

In the meantime, I wanted to pass on some information that was announced a week or so ago and which I became aware of just this week. Mentor Graphics has initiated a Displaced Worker Program to provide free training to customers who have lost thier jobs in the last 6 months. Back last Decemeber I had issued a challenge to the EDA vendors to do just this. I don’t know if this challenge had any affect; hopefully they did this because they thought it was the right thing to do.

So far Mentor is the only company that has done this, to my knowledge. I’ve personally had discussions with one other of the “Big 3″, so hopefully they will follow suit. Maybe Mentor’s offer will help prompt them.

What do you think? Should they do this?

harry the ASIC guy

Since conducting the Verification Methodology Poll and publishing the raw results last week, I’ve been planning to follow up with a post that digs a little deeper into the numbers. Things have gotten rather busy in the meantime, both at work and with organizing the SaaS and Cloud Computing EDA Roundtable for next week at DVCon. So I’ve let it slip a little.

Well, I noticed today that the verification methodology poll was referenced in a Cadence blog post by Adam Sherer. The results were somewhat mis-interpreted (in my opinion), so that kicked my butt to post my own interpretations to set the record straight. Says Adam:

According to the poll conducted by Harry Gries in his Harry the ASIC Guy blog, you should go “all in” on the OVM because it is the 2:1 favorite.

In fact, the raw results had VMM with 80 users and OVM with 125 users, a ratio of just over 1.5:1 (1.5625 to be exact). So the 2:1 ratio is not accurate. However, if you add in RVM/Vera users to the VMM numbers, and then add in AVM, eRM, and e users to the OVM numbers, that ratio is more like 1.8:1. Closer, but still not 2:1.

It also indicates that my poll says that “you should go ‘all in’ on the OVM”. I never said that nor does the poll say anything about what you “should do”. The data simply captures what people are planning on using next. If you are inclined to follow the majority, then perhaps OVM is the way to go. By contrast, there is nothing in the poll comparing the technical merits of the various methodologies. So, if you are inclined to make up your own mind, then you have some work to do and my poll won’t help you on that. You’re probably better off visiting JL Gray at Cool Verification.

No poll is perfect and it will be interesting to compare to DVCon and John Cooley polls to see if they are consistent. Here are a few other interesting stats that I pulled out of the poll results:

• 91% of respondents are using some sort of SystemVerilog methodology
• 10% are using both OVM and VMM (although I suspect many of these are consultants)
• 27% are still using e or Vera (more e than Vera)
• 4% are using ONLY VHDL or Verilog (this number may be low due to the skew of respondents towards advanced methodologies)

Again, I welcome you to download the raw data, which you can find in PDF format and as an Excel workbook, and draw your own conclusions.

harry the ASIC guy

I’ve been writing about Software-as-a-Service (SaaS) and Cloud Computing as relates to EDA for some time now. Then back in January I made a New Years resolution to organize a SaaS EDA roundtable at the 2009 Design and Verification Conference (DVCon).  About a month ago I asked for volunteers and several of you have stepped up to help. Now, just a week before DVCon, I’d like to formally announce the event.

The SaaS and Cloud Computing Roundtable will be held from 6:30 - 8:00 pm on Wed Feb 25th in the Monterey/Carmel rooms at the San Jose Doubletree Hotel. This is immediately following the DVCon reception down the hall, so grab a drink and a bite and then wander on over.

SaaS and Cloud Computing are 2 of the hottest trends in the Information Technology and software industries. Some EDA companies have already put their toes in the water. This roundtable will explore the following question: Are they trailblazing the future of the industry or are they chasing an empty fad?

The format will consist of 5 brief (< 10 minute) presentations from people involved in various perspectives in SaaS and cloud computing for EDA:

• Harry Gries (Design Methodology Consultant @ the ASIC guy)
• James Colgan (CEO @ Xuropa)
• Susan Peterson (Verification IP Marketing Manager @ Cadence)
• Jeremy Ralph (CEO @ PDTi)
• Bill Alexander (VP Marketing @ Blue Pearl Software)

This will be followed by an open, and hopefully lively, discussion.

I’m greatly looking forward to this event, especially since I get to collaborate with such a high-powered team and I have no idea what to expect. I truly believe that this could be one of the more interesting events at DVCon this year.

I hope to see many of you there.

harry the ASIC guy

Last week I initiated a poll of verification methodologies being used for functional verification of ASICs. Unlike other polls or surveys, this one was done in a very “open” fashion using a website that allows everyone to view the raw data. In this way, anyone can analyze the data and draw the conclusions that make sense to them, and those conclusions can be challenged and debated based on the data.

What happened next was interesting. Within 48 hours, the poll had received almost 200 responses from all over the world. It had garnered the attention of the big EDA vendors who solicited their supporters to vote. And, as a result, had became a focal point for shenanigans from over-zealous VMM and OVM fans.  I had several long nights digging through the data and now I am ready to present the results.

As promised, here is the raw data in PDF format and as an Excel workbook. The only change I have made is to remove the names of the individual 249 respondents.

In summary, the results are as follows:

(Note: The total is more than the 249 respondents because one respondent could be using more than one methodology.)

Regarding the big 3 vendors, the data shows a remarkable consistency with Gary Smith’s market share data. There are 85 respondents planning to use the Synopsys methodologies (VMM,RVM, or Vera) and there are 150 respondents planning to use the Mentor or Cadence methodologies (OVM, AVM, eRM, e). That represents 36% for Synopsys and 64% for Mentor/Cadence. Gary’s data shows Synopsys with 34% market share, Mentor with 35%, and Cadence with 30%.

I’ll share some more insights in upcoming posts. In the meantime, please feel free to offer any insights that you have through your comments. Remember, you too have access to the raw data. This invitation includes the EDA vendors. And feel free to challenge my conclusions … but back it up with data!

harry the ASIC guy

Quick update for everyone…

Regarding the Verification Methodology Poll I started the other day, I was able to go through the log files and identify the obvious malicious activity.  There was a string of deletes and changes of VMM votes to OVM/e votes. Then a string of deletes of OVM votes. I’m going to add back the original entries to make the data whole again.

In the meantime, the obvious malicious activity has subsided, and now there is only a trickle of clearly valid votes coming in. It’s just like listening for the popcorn to stop popping, when I see that the votes slow down to a certain rate, I’ll do my tallies and publish the results.

There have been questions raised regarding my motivations for doing this poll.  Some felt that I had some hidden agenda and some even thought that I was some sort of paid shill for one of the vendors. If you are a regular reader of my blog or if you know me, then you know that’s not true.  If you don’t know me, then ask around.

At the risk of sounding defensive, my goal was purely to conduct an “open” survey of the verification methodologies being used because this has been such a hot topic this past year, because DVCon is coming up and this would be good information, and because one of my readers suggested it and I thought it was a good idea.The idea of using Doodle was in order that everyone can view the raw data, something you rarely or never get to see when vendors and other organizations conduct polls and then release only the results that suit them best. In this way, anyone could analyze the raw data and draw the conclusions that made sense, and those conclusions could be challenged based on the raw data. The mistake I made was not realizing how easily those who, unlike me, actually had an agenda could vandalize the data.

There have also been questions raised regarding the validity of this poll and how “scientific” it is after all that has occurred. I think they are valid concerns and certainly, if I had to do this over again, I’d fix some things to prevent multiple voting and malicious behavior. Still, as I look at the interim results, they are similar to what I had expected. Each vendor lobbied their constituencies, so the playing field is level. It will be interesting to compare this result to DVCon surveys from the vendors, from DVCon itself, and from John Cooley to see if there is consistency.

Finally, to those of you who legitimately voted, I thank you for participating openly and I apologize that the results will always be subject to some doubt. I hope you don’t feel you wasted your time.

harry the ASIC guy

OK.  This will be short and sweet!

The poll I set up the other day was getting interesting and meaningful responses related to the verification methodologies being used. FORTUNATELY, I saved a snapshot of this data as it was coming in.

UNFORTUNATELY, I apparently did not do enough due diligence with respect to the Doodle site and neglected to realize that there is a way to vandalize the data.  Apparently, that is what started happening later in the day, to the point where this has now become a poll-war between the forces of OVM and the forces of VMM.  I won’t go so far as to name names, but you know who you are.

I feel bad for those who provided honest data.  Thank you for doing so and having faith in this poll. I have a snapshot that I feel is reasonably uncorrupted and I will still publish those results once I remove data that I feel was not entered in good faith.

I may have a way to find out if any of the EDA vendors were involved in this vandalism, so I encourage you to chill out and not make it any worse.

And if you were involved … GROW UP!!!

harry the ASIC guy

In response to a recent post regarding the verification survey on the DVCon website, Jeremy Ralph of PDTi expressed that he’d “be interested to know what proportion of the SV is OVM vs. VMM”, a question that was missing from the survey. Considering the whole kerfuffle concerning OVM and VMM over the last year, I thought this would be a good question for you, the ones really using the tools. I also thought it would be a good opportunity to try out this new Doodle survey tool I was told about.

So … I created the first ASIC guy survey on Doodle. That was very easy as was casting my own vote. Now it’s your turn.

HERE’S THE LINK

Feel free to leave a pseudonym if you wish to be anonymous. Make it funny, but keep it clean. And please don’t impersonate someone else.  I’ll know something is up if Aart votes for OVM

Also, please let other people know about this poll and ask them to vote.  The more votes we have, the more accurate the survey results. And it would be really cool if we can get more respondents online than DVCon had in person.

If this works well, I’ll continue to do this every so often. Feel free to provide suggestions for future polls.

harry the ASIC guy