About 27 minutes into the conference call, Sterling Autry asked why Cadence was estimating only $50M in operating income benefit considering Mentor’s operating income in 2007 was $120M. Indeed, $1.6B to acquire $50M in income seems like a poor deal indeed.

Kevin Palatnik’s response included the following, “the industry has had a history, from a customer perspective, of trying to get more and include features and not pay for it. So I think we just have to be able to demonstrate value to the customers. So I think, in the short term, I think, there is always the customers asking for the combination and not paying for it.”

The crux of the issue is simple math: 1 + 1 = ??? …how much will Cadence-Mentor be able to charge for their combined products?  If  1+1 > 1.5, then the combined company will be in pretty good shape.  If 1 + 1 < 1.5, then it will be difficult to “extract the value” of the acquisition. In that case, expect lots of layoffs, products being scrapped, and products being sold off.

From my experience, Kevin Palatnik is only partially correct that “the industry has had a history, from a customer perspective, of trying to get more and include features and not pay for it”. When I started with Synopsys in 1992, their flagship tool was Design Compiler. Synopsys added new features and voila…DC-Expert.  Then DC-Ultra. Now DC-Graphical. Each one sold at a premium to the predecessor and customers would pay for the upgrades.

But not without voicing their displeasure, both privately and also publicly on places like ESNUG. It often seemed arbitrary and self-serving to customers what Synopsys deemed an “update” (covered by their tool support) and what they deemed an “upgrade”.  And they felt they were being nickel-and-dimed.

On the other hand, people need to eat, and the EDA tool developers are no exception. They do not work for free. It seems unique to the EDA industry, that customers expect, once they buy a tool, to get any and all improvements to the product for free. This is not the case when I buy MS Office or most any other desktop application, but it is definitely a reality in EDA.

To add to the confusion, I can now download almost any desktop application I need for free as open-source (e.g. Open Office), or use it for free online (e.g. Google Docs), and get access to upgrades for free as well. This has changed customer expectations dramatically.

I’d like to know what you (EDA vendors and customers) think about this:

1. Should customers pay more for EDA tool enhancements or should they be part of the tool “support”?
2. How do you decide what is an “update” and what is an “upgrade”?

harry the ASIC guy

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This past Sunday was already a bad day.

My 4 year old son had decided this was the day he would be “age appropriate” and assert his independence. (I won’t capture the details here, lest some day he decide to run for President, only to have this post show up on CNN and derail his campaign). As a result, he was no longer going to Mathew’s party, and Joyce and I weren’t going to get that 2 hour break we needed.

Instead, while Nate pouted in the other room, I tried to catch up on writing my blog post for Monday. I was halfway done when the little green DSL light started to blink and the Internet light went dark. At first, no panic. I had become used to these intermittent outages, usually lasting 2-3 minutes. Time to grab a Cherry Coke Zero, check on Nate, and all would be well when I came back.

Not exactly. The lights were still out. After about an hour, I decided I needed to prepare myself for the ordeal that is “Verizon customer support”. I’d called Verizon about half a dozen times with similar issues and knew my day was not going to get any better.

1st: The dreaded Voice Response System. After 30 years of using a touch tone phone, I know where the keys are, and so do most people. But instead of getting my customer info from my CallerID and routing met to a real person, I had to speak my way through 7 levels of voice response.

“No”.

“My phone number”

“Yes”

“Repair and Tech Support”

“DSL”

“Yes”

“Windows”

2nd: The dreaded wait on hold while listening to really bad music. The only break in the music was the voice interrupting every 20 seconds to tell me that my wait would be less than 10 minutes. Oh, and that I could get online support at the Verizon Web site. Duh!

3rd: 25 minutes later, a real person, who needs to once again verify my phone number and identity. After explaining the problem, he insists that I reboot my modem before he continue. Of course, having used Verizon before and being a hardware designer, that was the first thing I did. But he would not proceed unless I gave it one more try.

4th: “Do you have filters on the other lines?” “No, my filters somehow magically removed themselves from where they were a few hours ago”. I was getting annoyed now.

5th: “Maybe it’s your jack”. I knew it was not, but he was not going to help me until I went through the motions. So he had me crawl under the desk and disconnect the modem and reconnect in the living room to another jack. This took me 5 minutes…no difference. Then another 5 minutes to put the modem back where it was.

6th: “Could it be a problem on Verizon’s end?” I asked. “We’d know immediately if we had a problem in your area and there is no problem”.

7th: “We’ll send a technician out tomorrow. Please hold while I get dispatch on the line. It will be about 5 minutes”.

8th: 15 minutes later, “the dispatch computer system is down, so I can’t put you in touch with them. I’ll put this in as high priority and you’ll be called back within half an hour to schedule an appointment”

9th: 2 hours later, I get a call that someone will be out between 8am and 5pm. Yah, like we’ll sit home waiting all day. I ask them to call ahead and they say they’ll call half an hour before they come.

10th: 15 minutes later I get an automated call telling me that my issue was resolved. I look at the blinking DSL light and the black Internet light and say “NO”. OK, they’ll still come out.

11th: Late afternoon Monday, Joyce, who is trying to launch a new business (shameless plug), calls to see where they are. (See 1-3 above, except add in talking to someone in India who evidently had never heard numbers spoken out loud). “They came by at 12:10 and nobody was there”. Not true, she was there. In any case, they had determined that the problem was on Verizon’s end, despite their original assurance to the contrary (see #6), and it was fixed. Indeed, solid green lights.

12th: Since Monday, the outage seems to have been resolved, but it’s back to the 2-3 minute intermittent outages. So I call up again and this time speak to Derrick. He reads or recites from memory the standard excuses:

“It could be thunderstorms”.

“This is LA…we have 2 thunderstorms a year.”

“Could be that we were doing an upgrade”

“Several times a day”?

In any case, I insist that they open a ticket and someone tell me why my connection is so intermittent and fix it.

“You’ll be contacted within 48 hours.” Ticket # 197518950

Stay Tuned.

harry the ASIC guy

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I googled this quote and it looks like it might have been Mark Twain or Abraham Lincoln or someone around those times. Whoever it was, I took their advice last week regarding the Cadence - Mentor acquisition, at least as far as anything on this blog was concerned. I have my views as to what will likely happen, but I’ve expressed them privately for the most part. Instead, I was listening to what others had to say.

And boy are there lots of opinions! As the dust settles, I’ve noticed something very interesting. There seems to be two camps.

In one camp are the people who are opposed to the merger or feel it won’t work. I must admit that this is the camp I am in, informed by 14 years in the EDA industry and bystander to several mergers, good and bad. The specific reasons have already been covered by others. They raise the spectre of Daisy/Cadnetix, pointing out significant product overlap, the difference of corporate cultures, FTC concerns, etc.

In the other camp are those who think this is a good idea, good for the industry, good for the companies, good for the shareholders. And they are mainly from the financial analyst and investment community. I admit, I have only a rudimentary understanding of the Wall Street side of the business, and the finances involved, so I ask you for your help to explain to me…

What do the Analysts Know that We Don’t Know?

harry the ASIC guy

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“To the unwary conference goer (and the EDA companies: my addition), the most important part of the VLSI design and verification problem, is tools. Choose the right tool, and you’ll be fine. Get it wrong, and you’ll never tape out a chip again…But far, far more important are the knowledge, skills, experience, and artistry of the people who use those tools. Peopleware, not Software or Hardware, is the most important VLSI body part.”

Having spent the last decade plus of my life in some way, shape, or form in the ASIC design consulting business, I could not agree with Tommy more. Never did my clients insist on using a particular tool. But almost always they’d ask for a consultant by name, because he had the “knowledge, skills, experience, and artistry” to get the job done.

And so, when I read the EE Times Story entitled EDA Vendors Get Squeezed on Two Fronts, I had to laugh. Here were the EDA vendors once again bemoaning the fact that the EDA industry is not able to “capture the value” (i.e. charge more for its products) that it justly deserves. The article referenced strategies such as royalties that have been rejected before. (After all, if you were a general contractor, would you pay a royalty to the company that made the hammer or the saw?)

Indeed, the EDA industry is largely a Cortical Homunculus, having a distorted view of how important it is to the success of it’s customers projects. Yes, the tools are a key enabler, but more important are the designers, the people using the tools. Through my years, I have had the honor or working with designers that I would take with me wherever I go, my A-Team. And it would not matter what tools they use, they’d be successful anyway they’d need to do it!!!

I’ve spent a good portion of the last year talking to people in the EDA industry, marketing people and sales people. They tell me things like the following:

• EDA is a dying business
• EDA companies are just trying to take market share from competitors
• There’s very little new in EDA
• All the innovation comes from the small companies

They are probably not listening to me, but just in case, here is my advice to the big EDA companies.

Try Something New!!!

Instead of stealing EDA share from eachother in the analog design or verification market, solve a new problem. Make our lives easier. In basic economic terms, there is only one type of company that “captures the value” of its offering, and that is the monopoly, the one-of-a-kind product that solves a must-solve problem.

harry the ASIC guy

(Postscript: I wrote this article prior to Cadence’s offer today to buy Mentor Graphics, but it relates to the same point. Instead of doing something new, the EDA vendor strategy is to take away, or in this case BUY, market share from its competitors.

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A well polished street magician got my attention at first at the Certess booth. After a few card tricks, finding the card I had picked out in the deck, he told me that it was as easy for him to find the card as it was for Certess to find the bugs in my design. Very clever!!! Someone must have been pretty proud they came up with that one. In any case, I’d had some exposure to Certess previously and was interested enough to invest 15 minutes.

Certess’ tool does something they call functional qualification. It’s kinda like ATPG fault grading for your verification suite. Basically, it seeds your DUT with potential bugs, then considers a bug “qualified” if the verification suite would cause the bug to be controlled and observed by a checker or assertion. If you have unqualified bugs (i.e. aspects of your design that are not tested), then there are holes in your verification suite.

This is a potentially useful tool since it helps you understand where the holes are in your verification suite. What next? Write more tests and run more vectors to get to those unqualified bugs. Ugh….more tests? I was hoping this would reduce the work, not increase it!!! This might be increasing my confidence, but life was so much simpler when I could delude myself that my test suite was actually complete.

Whereas the magician caught my attention at the Certess booth, I almost missed the Nusym booth as it was tucked away in the back corner of the Exhibit Hall. Actually, they did not really have a booth, just a few demo suites with a Nusymian guarding the entrance armed with nothing more than a RFID reader and a box of Twinkies. (I did not have my camera, so you’ll have to use your imagination). After all the attention they had gotten at DVCon and from Cooley, I was surprised that “harry the ASIC guy” could just walk up and get a demo in the suite.

(Disclaimer: There was no NDA required and I asked if this was OK to blog about and was told “Yup”, so here goes…)

The cool technology behind Nusym is the ability to do on-the-fly (during simulation) coverage analysis and reactively focused vector generation. Imagine a standard System Verilog testbench with constrained random generators and checkers and coverage groups defining your functional coverage goal. Using standard constrained random testing, the generators create patterns independent of what is inside the DUT and what is happening with the coverage monitors. If you hit actual coverage monitors or not, it doesn’t matter. The generators will do what they will do, perhaps hitting the same coverage monitors over and over and missing others altogether. Result: Lots of vectors run, insufficient functional coverage, more tests needed (random or directed).

The Nusym tool (no name yet) understands the DUT and does on-the-fly coverage analysis. It builds an internal model that includes all of the branches in your DUT and all of your coverage monitors. The constraint solver then generates patterns that try to get to the coverage monitors intentionally. In this way, it can get to deeply nested and hard to reach coverage points in a few vectors whereas constrained random may take a long time or never get there. Also, when you trigger a coverage monitor, it crosses it off the list and know it does not have to hit that monitor again. So the next vectors will try to hit something new. As compared to Certess, this is actually reducing the number of tests I need to write. In fact, they recommend just having a very simple generator that defines the basic constraints and focusing most of the energy on writing the coverage monitors. Result: Much fewer vectors run, high functional coverage. No more tests needed.

It sounds too good to be true, but it was obvious that these guys really believe in this tool and that they have something special. They are taking it slow. Nusym does not have a released product yet, but they have core technology with which they are working with a few customers/partners. They are also focusing on the core of the market, Verilog DUT, System Verilog Testbench. I would not throw out my current simulator just yet, but this seems like very unique and very powerful technology that can get coverage closure orders of magnitude faster than current solutions.

If anyone else saw their demo or has any comments, please chime in.

harry the ASIC guy

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FYI … You should also be able to meet James Colgan at the Bloggers Birds-of-a-Feather session at DAC.

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That’s what a puzzled ASIC designer would have asked with bewilderment if you mentioned the term “off-shoring” 10 years ago. But today the world is flat and off-shoring means global teams, working ’round the clock in 6 cities on 3 continents in 4 timezones on 1 chip. And it’s not just off-shoring and out-sourcing driving this globalization. Design teams for complex chips can have 100 - 150 designers doing tasks ranging from RTL design, verification, physical design, software and firmware development, mixed signal design, and so on. You just can’t find all the designers you need with the right expertise in one place or even in one company.

There are economic factors causing us to work remotely as well. Last week, American Airlines announced that they would start charging for baggage and other airlines are also raising their fares due to record oil prices. Companies, already watching the bottom line, are encouraging their people to travel less, just as they did several years ago after 9/11. Telecommuting has become accepted, even encouraged in many companies as a way to promote better employee lifestyles, save on office space, and be more “green”. As a result, for most of us, the days of the co-located design teams are as long gone as Hillary’s campaign.

Of course, these same ASIC and software design teams have designed and continue to design the technologies that enable effective collaboration between these dispersed teams. The high-speed networks that are the backbone that make it all possible. The IP routers. The graphics and specialized processors.

And let’s not forget the software applications that run on this hardware … Wikis for collaboration … WebEx, Sametime, and NetMeeting for remote meetings … Skype and Vonage for cheap global conferencing … video-conferencing … instant messaging … Twitter … Second Life … social networks like LinkedIn and FaceBook.

These technologies are impressive. Several years ago, I worked out of my home in Southern California, managing projects with team members in Silicon Valley, Arizona, Colorado, Washington State, Vancouver, Texas, Florida, Ottawa, and Bangalore. We conference called and held WebEx meetings. We worked on the same hosted environment through secure VPN. When necessary, we got up early (5 AM) or stayed up late (1 AM) to collaborate with team members half-way around the world. And these teams were able to get the job done as a result of their strong skills, hard work, and the technology that allowed them to work together. But, something was still missing and thanks to my sister-in-law I now realize what it was.

Face Time!

Our kids keep us pretty busy, so when Evelyn suggested that we need more “face time” with our kids, Joyce and I were flabbergasted. More face time? Don’t we already spend enough time getting them ready for school, dinner, or bed, taking them to this or that activity, helping with homework? Are there more than 24 hours in a day?

The truth is, although these parenting activities are important, they are not really face time. Face time is not about getting things done … it’s about getting to know one another better. Obviously, this makes a lot of sense if you are a parent, but you’re probably wondering what face time has to do with ASIC design? After all, this isn’t eHarmony or Parenting 101.

Several years ago, I attended a one-day class entitled Managing Virtually: What Works, taught by Lu Ellen Schafer of Global Savvy. Lu Ellen gave great advice on using email effectively, “drive-by-phoning” to stay in touch, collaboration tools, and especially on the difference between cultures (fascinating). But one thing stood out that she said. “Initial face-to-face interaction leads to greater remote communication.” She continued by pointing out that “informal email exchanges often do not happen among new team members until they meet face-to-face”. My friend Ron put it another way, “email is a great way to continue a relationship and a lousy way to start one”. And studies have shown this as well.

As for me, much of my day is consumed by discussions, meetings, and conference calls with co-workers, clients, and vendors. But that’s not really face time, even the face-2-face meetings. Face time is about getting to know one another and what the other person cares about. It’s something I’ve tried to do, but probably did not do enough. Go out to lunch. Go to a ballgame. Take a flight to meet a new person in the organization or on the team. Plan a team-building event and fly in the remote people. I’ve always found it easy to find excuses not to do these things … too busy … no budget … next time. But in the end, I always regret it because there is something missing. Something that feels like “trust”.

As a program manager, I recall three specific situations in which there was not enough trust because there was not enough face-time. In one case, there was some very nasty inter-personal conflict happening, but neither party trusted me enough to share their concerns until the situation was too far along. In another case, one remote team member felt he was being ignored by another remote team member, but he did not want to “bother” me with the issue. In the third instance, one team member decided to overrule another team member’s recommendations because “he knew better”. In that last case, once they met face-to-face, these two designers became a great tandem.

We all have to decide … Face Time or FaceBook?

This is not just a philosophical question but a practical one. I became aware a few days ago of a new social media company called Xuropa. From what I can gather from the website, the Xuropa Tradeshow Platform let’s you attend tradeshows at your desk. There are booths, suites, labs, demos … just like DAC, without the face time. So next year you may have a choice, DAC or eDAC?

As for me, I’m gonna have lunch on Friday with some people I haven’t seen in months. What about you?

harry the ASIC guy

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Perhaps you are a blogger or are thinking of becoming a blogger or know somebody who is a blogger. Perhaps you are a marketing director or just curious. Whatever your interest, you’ll want to come meet and engage with the bloggers who are growing in quantity, quality and industry influence:

• Quantity: A quick check of the DAC home page shows 17 industry blogs, and there are at least a dozen more, including yours truly.
• Quality: Topics as diverse as verification, design for test, analog design, semiconductors, memory, good design techniques, and standards, are discussed by design experts who actually use the tools and do the work.
• Influence: These blogs have influenced standardization efforts and challenged the status quo.

This event will be held in Rooms 201B and 201C at the Anaheim convention center on Wednesday, June 11 at 6pm.

I am helping to coordinate this session, so if you are planning to attend, just drop a quick email to harry {at} theASICguy {dot} com so we can get an idea for how large a group we will have. If you are a blogger and would like to present or be part of a panel, please let me know as well.

I hope to see and meet many of you there.

harry the ASIC guy

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Cadence won’t be there and I already talk to Synopsys and Mentor on a regular basis, so I’m planning on focusing on smaller companies with new technology. Here’s what’s on my list so far…

Nusym - They have some new “Path Tracing” technology that finds correlations between a constrained random testbench and hard-to-hit functional coverage points. With this knowledge, they claim to be able to modify the constraints to guide the simulation to hit the coverage points. The main benefit is in getting that last few % of functional coverage that can be difficult with unguided constrained random patterns.

Chip Estimate - Having been around for a few years and recently bought by Cadence, they are basically a portal where you can access 3rd party IP and use the information to do a rough chip floorplan. This allows you to estimate area, power, yield, etc. I’m real curious as to their business model and why Cadence bought them. At a minimum, it should be entertaining to see the hyper-competitive IP vendors present back-to-back at half hour intervals on the DAC floor.

I have a few others on my list, but there are so many small companies that it’s hard to go thru them all and decide what to see. That’s where I need your help.

What would you recommend seeing and why?

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