Posts Tagged ‘Accellera’

Why I’m a Blogger and Not an EDA Idol

Tuesday, July 7th, 2009

(WARNING: What you are about to hear is very disturbing. You may want to remove any children, pets, or small farm animals before listening to the audio in this blog post. You’ve been warned.)

Several years ago, I was driving home from a family vacation when I accidentally speed dialed my boss on the cell phone. His voice mail picked up just as I was singing in the car to my daughter. I had no idea what had occurred until a month later at a staff meeting when he got up in from of my team and my colleagues and played this audio track.

Now you know why I am not trying to become the next EDA Idol at this year’s Design Automation Conference!

Top BloggerFortunately, there is another tongue-in-cheek contest that I am honored to be part of, EDA’s Next Top Blogger.

In case you can’t make DAC this year, I’d like to introduce you to the fellow nominees because they are all great writers and experts in their domains. I encourage you to read these blogs and subscribe to the ones that you find valuable. And look beyond this list because there are many more out there.

Colin Warwick is a Product Marketing Manager at Agilent EEsof EDA group. Colin’s Signal Integrity blog is about signal integrity tips, tricks, and tutorial for multigigabit/s chip-to-chip data links. It includes videos (technical and humorous), tutorial articles, interactive calculators and polls, reviews, and product and event information.

John Busco is a Design Implementation Manager at NVidia. Blogging since 2005, John’s Semi-Blog shares high quality news and opinion about semiconductors and EDA. John is hands-on working in the trenches on the bleeding edge designs, so you can trust what he tells you.

Paul McLellan  has been an executive in EDA and Semiconductors with companies like VLSI Technologies, Compass, Ambit, Cadence,and on and on. His EDA Graffiti blog covers EDA and semiconductor, looking back to some history, analyzing the industry and looking where things are likely to end up. I always walk away from Paul’s blog posts with something to think about.

Daniel Nenni is also an EDA industry veteran with similarly impressive credentials. Although his Silicon Valley Blog is fairly new, Daniel writes like a verteran blogger, sharing his 25+ years of experience in semiconductor design and manufacture in an entertaining manner. He manages to share some of his personal life observations as well.

Karen Bartleson is Director of Community Marketing at Synopsys. Since November 2007, she has presented news, insights, and opinions on the topic of EDA standards in her ever popular The Standards Game blog. Karen is also spearheading Synopsys’ Conversation Central at DAC where you can exchange ideas with many of these same top bloggers (and many more) about how social media is changing the media landscape.

Frank Schirrmeister is Director of Product Marketing and System-Level Solutions at Synopsys. His A View From The Top blog is dedicated to System-Level Design and Embedded Software and deals with the technology and business aspects to get us to ESL and the next abstraction level eventually!

JL Gray is a hands-on verification consultant at Verilab. In his Cool Verification blog, which set the standard for independent blogging in EDA, JL shares this thoughts on hardware verification, the EDA industry, and related topics. JL spearheaded the EDA Blogger Birds-of-a-Feather session at DAC last year and sits on the ever popular Accellera Verification IP Technical Subcommittee.

I have 2 favors to ask. First, please check out some these wonderful bloggers (and some of the others you can find on David Lin’s EDA Blog Roll) who devote their evenings and weekends writing for free (well, about half of us) to bring you valuable information you can’t get anywhere else. Then, show your support by voting for your favorite blog and telling a friend or a co-worker about all this great content out there. Please vote for whoever you want, but remember, if I lose, I might have to sing next year. And you don’t want that!

(Note: The Denali site requires you to enter a Captcha phrase and also your valid email address in order to ensure that people only vote once. The email address WILL NOT be used for any other purpose, so please do not be dissuaded from voting because of this).

harry the ASIC guy

Update on SaaS/Cloud Roundtable & DVCon Day 1

Wednesday, February 25th, 2009

I’d like to update you on some new panel members for the SaaS and Cloud Computing EDA Roundtable and also give you some highlights from DVCon Day 1.

As previously reported, the roundtable will be held on Wednesday Feb 25th at 6:30pm in the Monterey/Carmel Rooms. We’ve picked up 2 additional panelists, Jean Brouwers and Bill Guthrie. Jean is an EDA industry veteran heavily into cloud computing and SaaS. Bill is Executive Vice President and Co-founder of Numetrics, a company that delivers its products using the SaaS model. This brings the total number of panelists to 7, so we should have many perspectives represented.

Here’s an update on DVCon Day 1:

Attendance at DVCon is down significantly this year. I don’t have exact numbers, but I’ve heard estimates on the order of half of last year. (Correction: By Day 3, there were 650 attendees which is ~80% of last year). Obviously the economy is a big factor. The exhibits session was probably 75% vendors and 25% attendees.

Lunch for approximately 150 attendees was sponsored by Accellera and included an overview of ongoing committee activities.and some informal polls on usage of Accleera standards. According to David Lin’s estimates OVL: 25%, UCIS: 40%, UPF: 10%, AMS: 2%, ITC: 5%, OCI: 2%, VHDL: 15%, SV: 80%, PSL: 10%. At one point the audience was asked how many had participated in the recent OVL survey and 1 person raised his hand.

I did not attend either the morning or afternoon tutorials due to work commitments in the morning and time spent at the exhibits in the afternoon. Some of the companies I spent time with include Gate Rocket, Achilles Test, and Synopsys. I’ll have some write ups on some of these visits shortly.

Finally, you can follow some of the live action on Twitter.

harry the ASIC guy

VMM on Questa & IUS Redux? Anything New Here?

Friday, December 5th, 2008

Considering what I’ve been hearing about the status of the Accellera VIP Subcommitee activity regarding OVM / VMM integration, I was rather surprised to see the following synchronized press releases from Mentor and Cadence yesterday:

As I understand, the Accellera VIP Subcommittee has just recently begun tackling the real crux issues regarding integrating the 2 methodologies such as:

  • Casting of disparate types
  • Synchronization of the simulation phases
  • Message reporting

My speculation is that Mentor and Cadence are just now formally announcing the availability of the “fixed up” VMM code that had previously leaked out in a blog post by JL Gray.

Does anyone out there know what’s really in this release? It would be good to hear directly from the vendors on this.

How about OVM on VCS? Has anybody been able to get that working?

harry the ASIC guy

Synopsys Calls, Mentor Raises

Thursday, July 24th, 2008

Not to be outdone, but with much less fanfare and ballyhoo than Synopsys’ donation of its Verification Methodology Manual (VMM) class library to the Accellera Verification IP (VIP) Technical Subcommittee, Mentor Graphics last week donated it’s Unified Coverage Database (UCDB) to the Accellera Unified Coverage Database Interoperability (UCIS) Technical Subcommittee.

Although not as hot a topic in the press and in the blogosphere, this represents a firm step forward in the standardization of the overall coverage driven verification methodology, whether you pray from the OVM or from the VMM hymnal. Whereas ratified or defacto standards already exist for the testbench languages, the requirements and coverage capture tools and formats are still proprietary to each of the 3 major vendors. This prevents the verification management tools of one vendor from being used with another vendor’s simulator. Having a UCDB standard will facilitate portability and enable more innovative solutions to be built by third parties on top of this standard.

Although Synopsys and Cadence have their own unique UCDB format, the basic elements of this standard should be much easier to agree upon without the political wrangling slowing the VIP subcommittee. I also think this is an opportunity for Synopsys, Mentor, and Cadence to show that they really can cooperate for the benefit of their customers and win back some of the goodwill lost in the OVM vs. VMM battle

harry the ASIC guy