harry … the ASIC guy

I had successfully avoided the zoo that is Monday at DAC and spent Tuesday zig-zagging the exhibit halls looking for my target list of companies to visit. (And former EDA colleagues, now another year older, greyer, and heavier). Interestingly enough, the first and last booths I visited on Tuesday seemed to offer opposite approaches to address the same issue. It was the best of times, it was the worst of times.

A well polished street magician got my attention at first at the Certess booth. After a few card tricks, finding the card I had picked out in the deck, he told me that it was as easy for him to find the card as it was for Certess to find the bugs in my design. Very clever!!! Someone must have been pretty proud they came up with that one. In any case, I’d had some exposure to Certess previously and was interested enough to invest 15 minutes.

Certess’ tool does something they call functional qualification. It’s kinda like ATPG fault grading for your verification suite. Basically, it seeds your DUT with potential bugs, then considers a bug “qualified” if the verification suite would cause the bug to be controlled and observed by a checker or assertion. If you have unqualified bugs (i.e. aspects of your design that are not tested), then there are holes in your verification suite.

This is a potentially useful tool since it helps you understand where the holes are in your verification suite. What next? Write more tests and run more vectors to get to those unqualified bugs. Ugh….more tests? I was hoping this would reduce the work, not increase it!!! This might be increasing my confidence, but life was so much simpler when I could delude myself that my test suite was actually complete.

Whereas the magician caught my attention at the Certess booth, I almost missed the Nusym booth as it was tucked away in the back corner of the Exhibit Hall. Actually, they did not really have a booth, just a few demo suites with a Nusymian guarding the entrance armed with nothing more than a RFID reader and a box of Twinkies. (I did not have my camera, so you’ll have to use your imagination). After all the attention they had gotten at DVCon and from Cooley, I was surprised that “harry the ASIC guy” could just walk up and get a demo in the suite.

(Disclaimer: There was no NDA required and I asked if this was OK to blog about and was told “Yup”, so here goes…)

The cool technology behind Nusym is the ability to do on-the-fly (during simulation) coverage analysis and reactively focused vector generation. Imagine a standard System Verilog testbench with constrained random generators and checkers and coverage groups defining your functional coverage goal. Using standard constrained random testing, the generators create patterns independent of what is inside the DUT and what is happening with the coverage monitors. If you hit actual coverage monitors or not, it doesn’t matter. The generators will do what they will do, perhaps hitting the same coverage monitors over and over and missing others altogether. Result: Lots of vectors run, insufficient functional coverage, more tests needed (random or directed).

The Nusym tool (no name yet) understands the DUT and does on-the-fly coverage analysis. It builds an internal model that includes all of the branches in your DUT and all of your coverage monitors. The constraint solver then generates patterns that try to get to the coverage monitors intentionally. In this way, it can get to deeply nested and hard to reach coverage points in a few vectors whereas constrained random may take a long time or never get there. Also, when you trigger a coverage monitor, it crosses it off the list and know it does not have to hit that monitor again. So the next vectors will try to hit something new. As compared to Certess, this is actually reducing the number of tests I need to write. In fact, they recommend just having a very simple generator that defines the basic constraints and focusing most of the energy on writing the coverage monitors. Result: Much fewer vectors run, high functional coverage. No more tests needed.

It sounds too good to be true, but it was obvious that these guys really believe in this tool and that they have something special. They are taking it slow. Nusym does not have a released product yet, but they have core technology with which they are working with a few customers/partners. They are also focusing on the core of the market, Verilog DUT, System Verilog Testbench. I would not throw out my current simulator just yet, but this seems like very unique and very powerful technology that can get coverage closure orders of magnitude faster than current solutions.

If anyone else saw their demo or has any comments, please chime in.

harry the ASIC guy

As I’ve been thinking a lot about Intellectual Property (IP) lately, I recently recalled a consulting project that I had led several years ago … I think it was 2002. The client was designing a processor chip that had a PowerPC core and several peripherals. The core and some of the peripherals were purchased IP and our job was to help with the verification and synthesis of the chip.

Shaun was responsible for the verification. As he started to verify one of the interfaces, he started to uncover bugs in the associated peripheral, which was purchased IP. We contacted the IP provider and were told most assuredly that it had all been 100% verified and silicon proven. But we kept finding bugs. Eventually, faced with undeniable proof of the poor quality of their IP, they finally fessed up. It seems the designer responsible for verifying the design had left the company half way through the project. They never finished the verification. Ugh 1!

Meanwhile, Suzanne was helping with synthesis of the chip, including the PowerPC core. No matter what she did, she kept finding timing issues in the core. Eventually, she dug into the PowerPC core enough to figure out what was going on. Latches! They had used latches in order to meet timing. All well and good, but the timing constraints supplied with the design did not reflect any of that. Ugh 2!

About a week later, I was called to a meeting with Gus, who was the client’s project lead’s boss’s boss. As I walked into his office, he said something that I’ll never forget …

“I’m beginning to believe that IP is a 4-letter word”.

How true. Almost every IP I have every encountered, be it a complex mixed-signal hard IP block, a synthesizable processor core, an IO library … they all have issues. How can an industry survive when the majority of the products don’t work? Do you think the HDTV market would be around if more than half the TVs did not work? Or any market. Yet this is tolerated for IP.

That is not to say that some IP providers don’t take quality seriously. Synopsys learned it’s lesson many years ago when it came out with a PCI core that was a quality disaster. To their credit, they took failure as a learning opportunity, developed a robust reuse methodology along with Mentor Graphics, and reintroduced a PCI core that is still in use today.

Still … no IP is 100% perfect out-of-the-box. IP providers need to have a relationship and business model with their customers that encourages open sharing of design flaws. This is a two-way street. The IP provider must notify its customers when it finds bugs, and the customer must inform the IP provider when it finds bugs. As an example, Synopsys and many other reputable IP providers will inform customers of any design issue immediately, a transparency that I could have only prayed for from the company providing IP to my client. In return, they need their customers support by reporting design issues to them. Sounds simple, right?

Maybe not. I had another client who discovered during verification that there was a bug in a USB Host Controller IP. They had debugged and corrected the problem already, so I asked the project manager if they had informed the IP provider yet. He refused. The rationale? He wanted his competition to have the buggy design while he had the only fix!

We, as users, play a role because we have a responsibility to report bugs for the good of all of us using the product. Karen Bartleson talks about a similar situation with her luggage provider, where customers are encouraged to send back their broken luggage in order to help the company improve their luggage design. The luggage gets better and better as a result.

So, besides reporting bugs and choosing IP carefully, what else can we as designers do to drive IP quality. I have one idea. One day, when I have some free time, I’d like to start an independent organization that would objectively assess and grade IP. We’d take it though all the tools and flows and look at all the views, logical and physical, and come out with an assessment. This type of open grading system would encourage vendors to improve their IP and would allow us to make more informed choices rather than playing Russian Roulette.

I’m half inclined to start one today … anybody with me?

harry the ASIC guy

Last Saturday night I went to a family Seder to celebrate the first night of Passover. You know, like in The Ten Commandments with Charlton Heston. As part of the Seder, we read a story of 4 sons, one wise, one contrary, one simple, and one unable to ask a question.

This got me thinking about some of the contrary ASIC designers I’ve worked with through the years … you know the type:

1. If everyone else wants to take road A, he wants to take road B.
2. If everyone else wants to take road B, he wants to take road C.
3. If you’ve got a plan, he’ll tell you why it won’t work.
4. Once he takes a stand on an issue, he’ll never give up.
5. He doesn’t really care what others think about him.
6. Every battle is worth fighting … to the death.

The contrarian ASIC designer can sap the energy and optimism out of a design team with all his negativity. Obviously, not good. So, why would anyone want to work with a contrarian?

Well, I’m here to tell you that the contrarian gets a bad rap and he can be a critical member of the team. First, some background…

Most law schools use a method of contrarian argument based upon the Socratic Method, that goes something like this:

• A legal decision to consider is chosen
• One student or the professor argues one interpretation
• Another student is assigned to argue the opposite position.

It does not matter what the individuals actually believe. They need to argue their assigned position as vigorously as they can. The goal is not for there to be a winner or loser in the argument. The goal is for the students to get the most complete and thorough understanding of the issue under consideration as possible. And only by giving both sides equal status can this be done. In the end, the law students emerge better prepared.

So, again, why would anyone want to work with a contrarian? In short, because the contrarian keeps the rest of us honest.

Consider the 6 behaviors of a contrarian that I mentioned earlier. Viewed within the context of law school argument, the contrarian is simply holding up his end of the bargain, to represent the opposite viewpoint. He’s the one most likely to find the holes that would otherwise eventually kill the project. Sure, he may find 9 holes that are not real for every real hole. But the one real hole he finds probably never would have been found by anyone else. In that sense, the contrarian is actually the ultimate optimist, because he’s the one trying the hardest to protect project success.

So, when you see that Contrarian on your project the next time, give him a hug…well, maybe not.

My friend Ron has a knack for recognizing revolutionary technologies before most of us. He was one of the first to appreciate the power of the browser and how it would transform the internet, previously used only by engineers and scientists. He was one of the first and best podcasters. And now he’s become a self-proclaimed New Media Evangelist, preaching the good news of Web 2.0 and making it accessible to “the rest of us”.

Most of us are familiar with mainstream Web 2.0 applications, whether we use them or our friends use them or our kids use them. Social and professional networks such as My Space, Facebook, and LinkedIn. Podcasts in iTunes. Blogging sites on every topic. Virtual worlds such as Second Life. Collaboration tools such as Wikipedia. File sharing sites such as Youtube and Flickr. Social bookmarking sites such as Digg and Technorati. Open source publishing tools such as Wordpress and Joomla. Using these technologies we’re having conversations, collaborating, and getting smarter in ways that were unimaginable just 5 years ago. Imagine, a rock climber in Oregon can share climbing techniques with a fellow climber in Alice Springs. And mostly for free, save for the cost of the internet connection.

When we think of Web 2.0, we tend to think of teenagers and young adults. But this technology was invented by us geeks and so it’s no surprise that the ASIC design world is also getting on-board. Here are some examples from the ASIC Design industry:

• Open Cores Design IP
• Cool Verification Blog
• DFT Digest
• ASIC / SoC Design Blog
• Verification Guild Forums
• LinkedIn / Yahoo group on ASIC Design
• OPML file that lists more blog feeds related to ASIC Design.

Social media is networking ASIC designer to ASIC designer enabling us to be smarter faster. But that’s not all. Many forward looking companies have recognized the opportunity to talk to their customers directly. About 6 months ago, Synopsys launched several blogs on its microsite. Xilinx also has a User Community and a blog. It’s great that this is happening, but does it really make much of a difference? Consider what I believe could be a watershed event:

A few months ago, JL Grey published a post on his Cool Verification blog entitled The Brewing Standards War - Verification Methodology. As expected, verification engineers chimed in and expressed their ardent opinions and viewpoints. What came next was not expected … stakeholders from Synopsys and Mentor joined the conversation. The chief VMM developer from Synopsys, Janick Bergeron, put forth information to refute certain statements that he felt were erroneous. A marketing manager from Mentor, Dennis Brophy, offered his views on why OVM was open and VMM was not. And Karen Bartleson, who participates in several standards committees for Synopsys, disclosed Synopsys’ plan to encourage a single standard by donating VMM to Accellera.

From what I’ve heard, this was one of the most viewed ASIC related blog postings ever (JL: Do you have any stats you can share?). But did it make a difference in changing the behavior of any of the protagonists? I think it did and here is why:

• This week at the Synopsys Users Group meeting in San Jose, the VMM / OVM issues were the main topic of questioning for CEO Aart DeGeus after his keynote address. And the questions picked up where they left off in the blog post…Will VMM ever be open and not just licensed? Is Synopsys trying to talk to Mentor and Cadence directly? If we have access to VMM, can we run it on other simulators besides VCS?
• Speaking to several Synopsoids afterwards, I discovered that the verification marketing manager referenced this particular Cool Verification blog posting in an email to an internal Synopsys verification mailing list. It seems he approved of some of the comments and wanted to make others in Synopsys aware of these customer views. Evidently he sees these opinions as valuable and valid. Good for him.
• Speaking to some at Synopsys who have a say in the future of VMM, I believe that Synopsys’ decision to donate VMM to Accellera has been influenced and pressured, at least in part, by the opinions expressed in the blog posting and the subsequent comments. Good for us.

I’d like to believe that the EDA companies and other suppliers are coming to recognize what mainstream companies have recognized … that the battle for customers is decreasingly being fought with advertisements, press releases, glossy brochures, and animated Power Point product pitches. Instead, as my friend Ron has pointed out, I am able to talk to “passionate content creators who know more about designing chips than any reporter could ever learn”, and find out what they think. Consider these paraphrased excerpts of the cluetrain manifesto : the end of business as usual:

• The Internet is enabling conversations among human beings that were simply not possible in the era of mass media. As a result, markets are getting smarter, more informed, more organized.
• People in networked markets have figured out that they get far better information and support from one another than from vendors.
• There are no secrets. The networked market knows more than companies do about their own products. And whether the news is good or bad, they tell everyone.
• Companies that don’t realize their markets are now networked person-to-person, getting smarter as a result and deeply joined in conversation are missing their best opportunity.
• Companies can now communicate with their markets directly. If they blow it, it could be their last chance.

In short, this ASIC revolution will not be televised!!!

harry the ASIC guy

I just attended Aart DeGeus’ keynote address at SNUG 2008 and there were two highlights:

1. Synopsys is back in the analog design market! Filling the gap in their product portfolio, they announced a new in-house developed product called Orion that is aiming directly at the Cadence users of Virtuoso. Orion is in beta right now and will work with Open Access. They did a canned demo and highlighted ease-of-use and productivity over Virtuoso.
2. Besides questions on Orion, all the other questions were regarding VMM / OVM and the path to getting a truly open standard verification methodology. Cliff Cummings and John Cooley asked the most direct questions on this topic, such as:

• Will VMM ever be truly open and not just licensed?
• Is there any attempt to speak directly to Mentor and Cadence to try to combine OVM and VMM?
• Can we use VMM with another System Verilog simulator?

Synopsys’ plan is to donate VMM to Accellera and have Accellera drive a standard verification methodology. When asked about working with Mentor/Cadence, Synopsys asked the designers to try to push them to the table within Accellera. I expect this battle will continue.

More later…. harry the ASIC guy

As a veteran ASIC designer … EDA applications engineer … consultant … project manager … biz dev manager … I’ve played a variety of key roles in the development of dozens of complex ASICs and SoCs. I’ve seen the industry from many perspectives … technical, managerial, financial … and I’ve seen what it takes to be successful and how little it takes to fail.

But, what fascinates me the most is the people. It’s the reason I left a desk job doing hands-on design at TRW to become an applications engineer at Synopsys working with people. And with the advent of new internet technologies (Open Source, Web2.0 …) the people are becoming even more important as they find new ways to work together and support each other. And turn the industry on it’s head.

Still, I don’t hear much about the people aspects of ASIC design from EDA vendors or trade publications … it doesn’t sell tools or subscriptions. And I don’t read much from the other industry blogs, many of them excellent for sure, as they focus more narrowly on rapidly evolving EDA technologies like verification.

For this reason, I started theASICguy.com … to share my insights into the people aspects of ASIC engineering for those who, like me, feel they are under-valued. I hope you find these insights to be thought-provoking and of practical value and I welcome your insights and comments. After all, several thousand heads are better than one

harry the ASIC guy