harry … the ASIC guy

One of the shortest but most relevant exchanges during the Cadence analyst call concerning the Mentor acquisition was an exchange between Sterling Autry of JP Morgan and Kevin Palatnik, CFO of Cadence.

About 27 minutes into the conference call, Sterling Autry asked why Cadence was estimating only $50M in operating income benefit considering Mentor’s operating income in 2007 was $120M. Indeed, $1.6B to acquire $50M in income seems like a poor deal indeed.

Kevin Palatnik’s response included the following, “the industry has had a history, from a customer perspective, of trying to get more and include features and not pay for it. So I think we just have to be able to demonstrate value to the customers. So I think, in the short term, I think, there is always the customers asking for the combination and not paying for it.”

The crux of the issue is simple math: 1 + 1 = ??? …how much will Cadence-Mentor be able to charge for their combined products?  If  1+1 > 1.5, then the combined company will be in pretty good shape.  If 1 + 1 < 1.5, then it will be difficult to “extract the value” of the acquisition. In that case, expect lots of layoffs, products being scrapped, and products being sold off.

From my experience, Kevin Palatnik is only partially correct that “the industry has had a history, from a customer perspective, of trying to get more and include features and not pay for it”. When I started with Synopsys in 1992, their flagship tool was Design Compiler. Synopsys added new features and voila…DC-Expert.  Then DC-Ultra. Now DC-Graphical. Each one sold at a premium to the predecessor and customers would pay for the upgrades.

But not without voicing their displeasure, both privately and also publicly on places like ESNUG. It often seemed arbitrary and self-serving to customers what Synopsys deemed an “update” (covered by their tool support) and what they deemed an “upgrade”.  And they felt they were being nickel-and-dimed.

On the other hand, people need to eat, and the EDA tool developers are no exception. They do not work for free. It seems unique to the EDA industry, that customers expect, once they buy a tool, to get any and all improvements to the product for free. This is not the case when I buy MS Office or most any other desktop application, but it is definitely a reality in EDA.

To add to the confusion, I can now download almost any desktop application I need for free as open-source (e.g. Open Office), or use it for free online (e.g. Google Docs), and get access to upgrades for free as well. This has changed customer expectations dramatically.

I’d like to know what you (EDA vendors and customers) think about this:

1. Should customers pay more for EDA tool enhancements or should they be part of the tool “support”?
2. How do you decide what is an “update” and what is an “upgrade”?

harry the ASIC guy

“Never miss an opportunity to keep your mouth shut”.

I googled this quote and it looks like it might have been Mark Twain or Abraham Lincoln or someone around those times. Whoever it was, I took their advice last week regarding the Cadence - Mentor acquisition, at least as far as anything on this blog was concerned. I have my views as to what will likely happen, but I’ve expressed them privately for the most part. Instead, I was listening to what others had to say.

And boy are there lots of opinions! As the dust settles, I’ve noticed something very interesting. There seems to be two camps.

In one camp are the people who are opposed to the merger or feel it won’t work. I must admit that this is the camp I am in, informed by 14 years in the EDA industry and bystander to several mergers, good and bad. The specific reasons have already been covered by others. They raise the spectre of Daisy/Cadnetix, pointing out significant product overlap, the difference of corporate cultures, FTC concerns, etc.

In the other camp are those who think this is a good idea, good for the industry, good for the companies, good for the shareholders. And they are mainly from the financial analyst and investment community. I admit, I have only a rudimentary understanding of the Wall Street side of the business, and the finances involved, so I ask you for your help to explain to me…

What do the Analysts Know that We Don’t Know?

harry the ASIC guy

Several weeks ago, Tommy Kelly published a blog post entitled DAC and the VLSI Homunculus :

“To the unwary conference goer (and the EDA companies: my addition), the most important part of the VLSI design and verification problem, is tools. Choose the right tool, and you’ll be fine. Get it wrong, and you’ll never tape out a chip again…But far, far more important are the knowledge, skills, experience, and artistry of the people who use those tools. Peopleware, not Software or Hardware, is the most important VLSI body part.”

Having spent the last decade plus of my life in some way, shape, or form in the ASIC design consulting business, I could not agree with Tommy more. Never did my clients insist on using a particular tool. But almost always they’d ask for a consultant by name, because he had the “knowledge, skills, experience, and artistry” to get the job done.

And so, when I read the EE Times Story entitled EDA Vendors Get Squeezed on Two Fronts, I had to laugh. Here were the EDA vendors once again bemoaning the fact that the EDA industry is not able to “capture the value” (i.e. charge more for its products) that it justly deserves. The article referenced strategies such as royalties that have been rejected before. (After all, if you were a general contractor, would you pay a royalty to the company that made the hammer or the saw?)

Indeed, the EDA industry is largely a Cortical Homunculus, having a distorted view of how important it is to the success of it’s customers projects. Yes, the tools are a key enabler, but more important are the designers, the people using the tools. Through my years, I have had the honor or working with designers that I would take with me wherever I go, my A-Team. And it would not matter what tools they use, they’d be successful anyway they’d need to do it!!!

I’ve spent a good portion of the last year talking to people in the EDA industry, marketing people and sales people. They tell me things like the following:

• EDA is a dying business
• EDA companies are just trying to take market share from competitors
• There’s very little new in EDA
• All the innovation comes from the small companies

They are probably not listening to me, but just in case, here is my advice to the big EDA companies.

Try Something New!!!

Instead of stealing EDA share from eachother in the analog design or verification market, solve a new problem. Make our lives easier. In basic economic terms, there is only one type of company that “captures the value” of its offering, and that is the monopoly, the one-of-a-kind product that solves a must-solve problem.

harry the ASIC guy

(Postscript: I wrote this article prior to Cadence’s offer today to buy Mentor Graphics, but it relates to the same point. Instead of doing something new, the EDA vendor strategy is to take away, or in this case BUY, market share from its competitors.

OK … I’m registered to go to DAC for at least one day, maybe two. I’ll definitely be there on Tuesday and probably Wednesday evening for a Blogging “Birds-of-a-Feather” session that JL Gray is setting up. Besides hitting the forums and other activities, I’ll have about half a day to attack the exhibit floor or the “suites” to look at some new technology. If you want to meet up, drop me an email and we can arrange something.

Cadence won’t be there and I already talk to Synopsys and Mentor on a regular basis, so I’m planning on focusing on smaller companies with new technology. Here’s what’s on my list so far…

Nusym - They have some new “Path Tracing” technology that finds correlations between a constrained random testbench and hard-to-hit functional coverage points. With this knowledge, they claim to be able to modify the constraints to guide the simulation to hit the coverage points. The main benefit is in getting that last few % of functional coverage that can be difficult with unguided constrained random patterns.

Chip Estimate - Having been around for a few years and recently bought by Cadence, they are basically a portal where you can access 3rd party IP and use the information to do a rough chip floorplan. This allows you to estimate area, power, yield, etc. I’m real curious as to their business model and why Cadence bought them. At a minimum, it should be entertaining to see the hyper-competitive IP vendors present back-to-back at half hour intervals on the DAC floor.

I have a few others on my list, but there are so many small companies that it’s hard to go thru them all and decide what to see. That’s where I need your help.

What would you recommend seeing and why?

On her Standards Game Blog  today, Karen Bartleson announced that Accellera is forming a subcommittee to define a standard for verification interoperability.  That is, to try to settle the VMM / OVM war.  As I have stated before in comments on JL Gray’s Cool Veification Blog, this is the right move because it give us input into the process, rather than just the EDA vendors controlling the process for their own benefit.  Also, as I argued in a previous post entitled “The Revolution Will Not Be Televised”, the influence and pressure of the verification community and especially the Cool Verification Blog were at least in part responsible.

Of course, Synopsys will tell you that they are just doing the right thing

It’s not clear how Cadence and Mentor will respond.  Hopefully they’ll join the effort.  Let’s keep the pressure on.

I just attended Aart DeGeus’ keynote address at SNUG 2008 and there were two highlights:

1. Synopsys is back in the analog design market! Filling the gap in their product portfolio, they announced a new in-house developed product called Orion that is aiming directly at the Cadence users of Virtuoso. Orion is in beta right now and will work with Open Access. They did a canned demo and highlighted ease-of-use and productivity over Virtuoso.
2. Besides questions on Orion, all the other questions were regarding VMM / OVM and the path to getting a truly open standard verification methodology. Cliff Cummings and John Cooley asked the most direct questions on this topic, such as:

• Will VMM ever be truly open and not just licensed?
• Is there any attempt to speak directly to Mentor and Cadence to try to combine OVM and VMM?
• Can we use VMM with another System Verilog simulator?

Synopsys’ plan is to donate VMM to Accellera and have Accellera drive a standard verification methodology. When asked about working with Mentor/Cadence, Synopsys asked the designers to try to push them to the table within Accellera. I expect this battle will continue.

More later…. harry the ASIC guy