harry … the ASIC guy

Several weeks ago, Tommy Kelly published a blog post entitled DAC and the VLSI Homunculus :

“To the unwary conference goer (and the EDA companies: my addition), the most important part of the VLSI design and verification problem, is tools. Choose the right tool, and you’ll be fine. Get it wrong, and you’ll never tape out a chip again…But far, far more important are the knowledge, skills, experience, and artistry of the people who use those tools. Peopleware, not Software or Hardware, is the most important VLSI body part.”

Having spent the last decade plus of my life in some way, shape, or form in the ASIC design consulting business, I could not agree with Tommy more. Never did my clients insist on using a particular tool. But almost always they’d ask for a consultant by name, because he had the “knowledge, skills, experience, and artistry” to get the job done.

And so, when I read the EE Times Story entitled EDA Vendors Get Squeezed on Two Fronts, I had to laugh. Here were the EDA vendors once again bemoaning the fact that the EDA industry is not able to “capture the value” (i.e. charge more for its products) that it justly deserves. The article referenced strategies such as royalties that have been rejected before. (After all, if you were a general contractor, would you pay a royalty to the company that made the hammer or the saw?)

Indeed, the EDA industry is largely a Cortical Homunculus, having a distorted view of how important it is to the success of it’s customers projects. Yes, the tools are a key enabler, but more important are the designers, the people using the tools. Through my years, I have had the honor or working with designers that I would take with me wherever I go, my A-Team. And it would not matter what tools they use, they’d be successful anyway they’d need to do it!!!

I’ve spent a good portion of the last year talking to people in the EDA industry, marketing people and sales people. They tell me things like the following:

• EDA is a dying business
• EDA companies are just trying to take market share from competitors
• There’s very little new in EDA
• All the innovation comes from the small companies

They are probably not listening to me, but just in case, here is my advice to the big EDA companies.

Try Something New!!!

Instead of stealing EDA share from eachother in the analog design or verification market, solve a new problem. Make our lives easier. In basic economic terms, there is only one type of company that “captures the value” of its offering, and that is the monopoly, the one-of-a-kind product that solves a must-solve problem.

harry the ASIC guy

(Postscript: I wrote this article prior to Cadence’s offer today to buy Mentor Graphics, but it relates to the same point. Instead of doing something new, the EDA vendor strategy is to take away, or in this case BUY, market share from its competitors.

I had successfully avoided the zoo that is Monday at DAC and spent Tuesday zig-zagging the exhibit halls looking for my target list of companies to visit. (And former EDA colleagues, now another year older, greyer, and heavier). Interestingly enough, the first and last booths I visited on Tuesday seemed to offer opposite approaches to address the same issue. It was the best of times, it was the worst of times.

A well polished street magician got my attention at first at the Certess booth. After a few card tricks, finding the card I had picked out in the deck, he told me that it was as easy for him to find the card as it was for Certess to find the bugs in my design. Very clever!!! Someone must have been pretty proud they came up with that one. In any case, I’d had some exposure to Certess previously and was interested enough to invest 15 minutes.

Certess’ tool does something they call functional qualification. It’s kinda like ATPG fault grading for your verification suite. Basically, it seeds your DUT with potential bugs, then considers a bug “qualified” if the verification suite would cause the bug to be controlled and observed by a checker or assertion. If you have unqualified bugs (i.e. aspects of your design that are not tested), then there are holes in your verification suite.

This is a potentially useful tool since it helps you understand where the holes are in your verification suite. What next? Write more tests and run more vectors to get to those unqualified bugs. Ugh….more tests? I was hoping this would reduce the work, not increase it!!! This might be increasing my confidence, but life was so much simpler when I could delude myself that my test suite was actually complete.

Whereas the magician caught my attention at the Certess booth, I almost missed the Nusym booth as it was tucked away in the back corner of the Exhibit Hall. Actually, they did not really have a booth, just a few demo suites with a Nusymian guarding the entrance armed with nothing more than a RFID reader and a box of Twinkies. (I did not have my camera, so you’ll have to use your imagination). After all the attention they had gotten at DVCon and from Cooley, I was surprised that “harry the ASIC guy” could just walk up and get a demo in the suite.

(Disclaimer: There was no NDA required and I asked if this was OK to blog about and was told “Yup”, so here goes…)

The cool technology behind Nusym is the ability to do on-the-fly (during simulation) coverage analysis and reactively focused vector generation. Imagine a standard System Verilog testbench with constrained random generators and checkers and coverage groups defining your functional coverage goal. Using standard constrained random testing, the generators create patterns independent of what is inside the DUT and what is happening with the coverage monitors. If you hit actual coverage monitors or not, it doesn’t matter. The generators will do what they will do, perhaps hitting the same coverage monitors over and over and missing others altogether. Result: Lots of vectors run, insufficient functional coverage, more tests needed (random or directed).

The Nusym tool (no name yet) understands the DUT and does on-the-fly coverage analysis. It builds an internal model that includes all of the branches in your DUT and all of your coverage monitors. The constraint solver then generates patterns that try to get to the coverage monitors intentionally. In this way, it can get to deeply nested and hard to reach coverage points in a few vectors whereas constrained random may take a long time or never get there. Also, when you trigger a coverage monitor, it crosses it off the list and know it does not have to hit that monitor again. So the next vectors will try to hit something new. As compared to Certess, this is actually reducing the number of tests I need to write. In fact, they recommend just having a very simple generator that defines the basic constraints and focusing most of the energy on writing the coverage monitors. Result: Much fewer vectors run, high functional coverage. No more tests needed.

It sounds too good to be true, but it was obvious that these guys really believe in this tool and that they have something special. They are taking it slow. Nusym does not have a released product yet, but they have core technology with which they are working with a few customers/partners. They are also focusing on the core of the market, Verilog DUT, System Verilog Testbench. I would not throw out my current simulator just yet, but this seems like very unique and very powerful technology that can get coverage closure orders of magnitude faster than current solutions.

If anyone else saw their demo or has any comments, please chime in.

harry the ASIC guy

Every year on March 19th, the swallows wing their way back to San Juan Capistrano. Just up the road in Anaheim, designers from around the world will fly in for the 45th Annual Design Automation Conference, held June 8th - 13th. How appropriate will it be then, when EDA and ASIC design bloggers flock to the 1st annual DAC Birds-of-a-Feather session on blogging?

Perhaps you are a blogger or are thinking of becoming a blogger or know somebody who is a blogger. Perhaps you are a marketing director or just curious. Whatever your interest, you’ll want to come meet and engage with the bloggers who are growing in quantity, quality and industry influence:

• Quantity: A quick check of the DAC home page shows 17 industry blogs, and there are at least a dozen more, including yours truly.
• Quality: Topics as diverse as verification, design for test, analog design, semiconductors, memory, good design techniques, and standards, are discussed by design experts who actually use the tools and do the work.
• Influence: These blogs have influenced standardization efforts and challenged the status quo.

This event will be held in Rooms 201B and 201C at the Anaheim convention center on Wednesday, June 11 at 6pm.

I am helping to coordinate this session, so if you are planning to attend, just drop a quick email to harry {at} theASICguy {dot} com so we can get an idea for how large a group we will have. If you are a blogger and would like to present or be part of a panel, please let me know as well.

I hope to see and meet many of you there.

harry the ASIC guy