harry … the ASIC guy

In response to a recent post regarding the verification survey on the DVCon website, Jeremy Ralph of PDTi expressed that he’d “be interested to know what proportion of the SV is OVM vs. VMM”, a question that was missing from the survey. Considering the whole kerfuffle concerning OVM and VMM over the last year, I thought this would be a good question for you, the ones really using the tools. I also thought it would be a good opportunity to try out this new Doodle survey tool I was told about.

So … I created the first ASIC guy survey on Doodle. That was very easy as was casting my own vote. Now it’s your turn.

HERE’S THE LINK

Feel free to leave a pseudonym if you wish to be anonymous. Make it funny, but keep it clean. And please don’t impersonate someone else.  I’ll know something is up if Aart votes for OVM

Also, please let other people know about this poll and ask them to vote.  The more votes we have, the more accurate the survey results. And it would be really cool if we can get more respondents online than DVCon had in person.

If this works well, I’ll continue to do this every so often. Feel free to provide suggestions for future polls.

harry the ASIC guy

I came across some interesting survey results from the 2007 and 2008 DVCon. Keep in mind, like with any survey, results are skewed based on attendees, which tend to be verification engineers who tend to be using the more advanced methods than the general population. Hence, I’d put more weight on the trends than on the absolute numbers.

1) Which is your primary design language?
                2007     2008
Verilog          56%      55%
VHDL              9%      10%
C/C++            13%      12%
SystemC           9%       8%
SystemVerilog    13%      15%

2 Which primary verification language do you use?
                2007     2008
C/C+             18%      18%
e                 7%       5%
OpenVera          4%       4%
Verilog          28%      25%
VHDL              7%       7%
System C         13%      11%
SystemVerilog    23%      30%

3) Which primary verification language do you plan to
use for your next design?
                2007     2008
C/C++            16%      15%
e                 5%       4%
OpenVera          1%       2%
Verilog          16%      16%
VHDL              4%       5%
SystemC          15%      11%
SystemVerilog    43%      47%

4) Which primary property specification (assertion-based
verification) language do you use?
                2007     2008
Verilog          31%      34%
VHDL              7%       6%
PSL              12%      10%
SVA              49%      50%

Thoughts?

harry the ASIC guy

A friend just made me aware of a new “No EDA Tool Purchase” plan from Blue Pearl Software.

Hmmm …. sounds like Software-as-a-Service with none of the benefits for customer or vendor:

• Customer still needs to generate a PO. (By old school thinking, that’s a way to “qualify” the customer.  New school, that’s a barrier to customers actually trying your tool).
• Still need to install software at the customer’s site. (”What OS are you running? What version? Do you have the right version of ActiveTcl installed?” Ugh!!!)
• Still need to incur the cost of travel. (Nuff said)
• Have to get the work done in a 2-day fixed window (Is anything ever done in this short a timeframe? If not, then what?)
• Have to schedule to when the AE is available, so customer can’t do this on a moment’s notice. (How does a month from now sound … Oh … never mind … AE is out that week … how about the following week).
• Need to dedicate an AE full-time per customer. (What’s he do while the customer goes to meetings?)

Instead, why not:

• make the software available online
• let the designer upload his RTL and work from his desk
• let the AE work remotely from his office

No PO required. No installation issues. No travel. Easy to schedule and staff and extend if needed. (See what Xuropa is doing). Heck, why not just sell the software that way while you’re at it.

Maybe I’m missing something.  Maybe someone from Blue Pearl wants to explain what the thinking behind this is.

And if you’re interested in topics like this, stay tuned for more on the upcoming SaaS EDA Roundtable at DVCon.

harry the ASIC guy

How much would you pay to be in the audience for some of the most thought provoking conference presentations from some of the greatest minds in the world. Here’s your ticket.

It’s FREE … completely FREE.

No registration. No airplanes. No hotels. No rental car.

While you sit at home, on a Sunday afternoon, drinking a beer.

Of course, nothing can completely replace the face to face interaction at a real conference. But in these “hard times” and with the technologies like flip cameras making video ubiquitous, it’s a damn good alternative.

It should be interesting to see what comes of DVCon, SNUG, and DAC this year in this regard. My prediction is that you will see an explosion of coverage. Videos (authorized and pirated) of presentations and floor and suite demos and interviews on flip cameras. Blog posts. Twitter feeds with customer hashtags.

What do you think?

harry the ASIC guy

I’m arranging for a meeting room for an EDA SaaS roundtable discussion at DVCon in San Jose sometime between Feb 24 - Feb 26.  What I need is some volunteers to help me organize this event. For instance:

• What will be the format and topics for discussion?
• Who will be the key participants?
• What do we hope to get out of this event?
• Who is bringing the refreshments?

If you are concerned about the time commitment, I think it will be fairly minimal.  I was part of a group that helped organize the Blogger Birds of a Feather session at DAC last year and it took about an hour on 3-4 Saturday mornings.

If you would like to be part of the planning for this event, please let me know.

Also, if your company would like to be part of the roundtable, please let me know as well.

harry the ASIC guy