harry … the ASIC guy

That’s the question that everyone was asking last week when Oasys Design Systems came out of stealth mode with a “chip synthesis” tool they claim leaves Synopsys’ Design Compiler and other synthesis tools in the dust. According to Sanjiv Kaul, Chairman of Oasys and former VP of Synopsys’ Implementation Business Unit, RealTime Designer can synthesize full chips up to 100 million gates in a single run, and do so 20x faster with smaller memory requirements and achieving better quality of results. Oh, and it also produces a legalized cell placement that can be taken forward into detailed routing.

Well, I had 3 different reactions to these claims:

1. “Too good to be true!”

This was also the most common reaction I heard from fellow designers when I told them of the Oasys claims. It was my own reaction a month or so ago when I first spoke to Oasys about their technology. (To tell the truth, I was wondering what they were smoking.) Paul McLellan, as of last week a blogger for Oasys, indicated that disbelief was the most common reaction heard from people Oasys talks to about this product. Steve Meier, former VP of R&D for IC Compiler at Synopsys, said the same thing on Twitter and added some specific questions for Oasys to answer. Even one of the Oasoids (is it to early to coin that phrase) acknowledged to me privately that he was incredulous when he was first approached months ago to join the team. I guess he was convinced enough to join.

2. “I’ve seen this movie before, and I know how it ends.”

That was my second reaction. After all, there were Synopsys killers before. Ambit (out of which, by the way, came most of the developers of the Oasys tool) was the first big threat. They had a better QOR (quality of results) by many accounts, but Synopsys responded quickly to stave them off. Then came Get2Chip. Similar story. Cadence’s RTL Compiler, which combines technology from both Ambit and Get2Chip, is well regarded by many but still it has a very small market share. Bottom line, nobody ever got fired for choosing Design Compiler, so it’s hard to imagine a mass migration. Still, if the Oasys claims are true, they’d have a much more compelling advantage than Ambit or Get2Chip ever had.

3. “Synthesis? Who cares about synthesis?”

That’s my third reaction. Verification is the #1 problem for ASIC design teams. DFM is a critical issue. ESL and C-synthesis are starting to take off. RTL synthesis addresses none of these big problems or opportunities. It’s a solved problem. Indeed, many design flows just do a “quick and dirty” synthesis in order to get a netlist in to place and route where real timing can be seen and a good placement performed. I hear very few people complaining about synthesis, so I wonder who is going to spend money in a tight economy on something that just “ain’t broken”. True, synthesis may be a bottleneck for 100M gate ASICs, but how many companies are doing those and can those companies alone support Oasys. If you talk to Oasys, however, they feel that the availability of such fast synthesis will change the way people design, creating a “new platform”. I’m not sure I see that, but perhaps they are smarter than me.

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OK, so that’s my first 3 thoughts regarding Oasys design. I’ll be getting a better look at them at DAC and will share what I learn in some upcoming blog posts. Please feel free to share your thoughts here as well. Between us, we can hopefully decide if this Oasys is real or a mirage.

harry the ASIC guy

By Narendra (Nari) Shenoy, Technical Program Co-Chair, 46th DAC

Each year, around this time, the electronic design industry and academia meticulously prepare to showcase the latest research and technologies at the Design Automation Conference. For the casual attendee, after a few years the difference between the conferences of years past begins to dim. If you are one of them, allow me to dispel this notion and invite you to look at what is different this year.

For starters, we will be in the beautiful city of San Francisco from July 26-31. The DAC 2009 program, as in previous years, has been thoughtfully composed from using two approaches. The bottom up approach selects technical papers from a pool of submissions using a rigorous review process. This ensures that only the best technical submissions are accepted. For 2009, we see an increasing focus on research towards system level design, low power design and analysis, and physical design and manufacturability. This year, a special emphasis for the design community has been added to the program, with a User Track that runs throughout the conference. The new track, which focuses on the use of EDA tools, attracted 117 submissions reviewed by a committee made up of experienced tool users from the industry. The User Track features front end and back end sessions and a poster session that allows a perfect opportunity to interact with presenters and other DAC attendees. In addition to the traditional EDA professionals, we invite all practitioners in the design community – design tool users, hardware and software designers, application engineers, consultants, and flow/methodology developers, to come join us.

This first approach is complemented by a careful top-down selection of themes and topics in the form of panels, special sessions, keynote sessions, and management day events. The popular CEO panel returns to DAC this year as a keynote panel. The captains of the EDA industry, Aart deGeus (Synopsys), Lip-Bu Tan (Cadence) and Walden Rhines (Mentor) will explore what the future holds for EDA. The keynote on Tuesday by Fu-Chieh Hsu (TSMC), will discuss alignment of business and technology models to overcome design complexity. William Dally (Nvidia and Stanford) will present the challenges and opportunities that throughput computing provides to the EDA world in his keynote on Wednesday. Eight panels on relevant areas are spread across the conference. One panel explores whether the emphasis on Design for Manufacturing is a differentiator or a distraction. Other panels focus on a variety of themes such as confronting hardware-dependent software design, analog and mixed signal verification challenges, and various system prototyping approaches. The financial viability of Moore’s law is explored in a panel, while another panel explores the role of statistical analysis in several fields, including EDA. Lastly, we have a panel exploring the implications of recent changes in the EDA industry from an engineer’s perspective.

Special technical sessions will deal with a wide variety of themes such as preparing for design at 22nm, designing circuits in the face of uncertainty, verification of large systems on chip, bug-tracking in complex designs, novel computation models and multi-core computing. Leading researchers and industry experts will present their views on each of these topics.

Management day includes topics that tackle challenges and decision making in a complex technology and business environment. The current “green” trend is reflected in a slate of events during the afternoon of Thursday July 30th. We start with a special plenary that explores green technology and its impact on system design, public policy and our industry. A special panel investigates the system level power design challenge and finally a special session considers technologies for data centers.

Rather than considering it a hindrance to attendance, the prolonged economic malaise this year should provide a fundamental reason to participate at DAC. As a participant in the technical program, DAC offers an opportunity to share your research and win peer acclaim. As an exhibitor, it is an ideal environment to demonstrate your technology and advance your business agenda. As an attendee, you cannot afford to miss the event where “electronic design meets”. DAC provides an unparalleled chance to network and learn about advances in electronic design for everyone. Won’t you join us at the Moscone Center at the end of the month?

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This year’s DAC will be held July 26-31 at the Moscone Center in San Francisco. Register today at www.dac.com. Note also that there are 600 free DAC passes being offered courtesy of the DAC Fan Club (Atrenta, Denali, Springsoft) for those who have no other means to attend.

(WARNING: What you are about to hear is very disturbing. You may want to remove any children, pets, or small farm animals before listening to the audio in this blog post. You’ve been warned.)

Several years ago, I was driving home from a family vacation when I accidentally speed dialed my boss on the cell phone. His voice mail picked up just as I was singing in the car to my daughter. I had no idea what had occurred until a month later at a staff meeting when he got up in from of my team and my colleagues and played this audio track.

Now you know why I am not trying to become the next EDA Idol at this year’s Design Automation Conference!

Fortunately, there is another tongue-in-cheek contest that I am honored to be part of, EDA’s Next Top Blogger.

In case you can’t make DAC this year, I’d like to introduce you to the fellow nominees because they are all great writers and experts in their domains. I encourage you to read these blogs and subscribe to the ones that you find valuable. And look beyond this list because there are many more out there.

Colin Warwick is a Product Marketing Manager at Agilent EEsof EDA group. Colin’s Signal Integrity blog is about signal integrity tips, tricks, and tutorial for multigigabit/s chip-to-chip data links. It includes videos (technical and humorous), tutorial articles, interactive calculators and polls, reviews, and product and event information.

John Busco is a Design Implementation Manager at NVidia. Blogging since 2005, John’s Semi-Blog shares high quality news and opinion about semiconductors and EDA. John is hands-on working in the trenches on the bleeding edge designs, so you can trust what he tells you.

Paul McLellan  has been an executive in EDA and Semiconductors with companies like VLSI Technologies, Compass, Ambit, Cadence,and on and on. His EDA Graffiti blog covers EDA and semiconductor, looking back to some history, analyzing the industry and looking where things are likely to end up. I always walk away from Paul’s blog posts with something to think about.

Daniel Nenni is also an EDA industry veteran with similarly impressive credentials. Although his Silicon Valley Blog is fairly new, Daniel writes like a verteran blogger, sharing his 25+ years of experience in semiconductor design and manufacture in an entertaining manner. He manages to share some of his personal life observations as well.

Karen Bartleson is Director of Community Marketing at Synopsys. Since November 2007, she has presented news, insights, and opinions on the topic of EDA standards in her ever popular The Standards Game blog. Karen is also spearheading Synopsys’ Conversation Central at DAC where you can exchange ideas with many of these same top bloggers (and many more) about how social media is changing the media landscape.

Frank Schirrmeister is Director of Product Marketing and System-Level Solutions at Synopsys. His A View From The Top blog is dedicated to System-Level Design and Embedded Software and deals with the technology and business aspects to get us to ESL and the next abstraction level eventually!

JL Gray is a hands-on verification consultant at Verilab. In his Cool Verification blog, which set the standard for independent blogging in EDA, JL shares this thoughts on hardware verification, the EDA industry, and related topics. JL spearheaded the EDA Blogger Birds-of-a-Feather session at DAC last year and sits on the ever popular Accellera Verification IP Technical Subcommittee.

I have 2 favors to ask. First, please check out some these wonderful bloggers (and some of the others you can find on David Lin’s EDA Blog Roll) who devote their evenings and weekends writing for free (well, about half of us) to bring you valuable information you can’t get anywhere else. Then, show your support by voting for your favorite blog and telling a friend or a co-worker about all this great content out there. Please vote for whoever you want, but remember, if I lose, I might have to sing next year. And you don’t want that!

(Note: The Denali site requires you to enter a Captcha phrase and also your valid email address in order to ensure that people only vote once. The email address WILL NOT be used for any other purpose, so please do not be dissuaded from voting because of this).

harry the ASIC guy

I mentioned a few weeks ago that I am wrapping up a project with one of my clients and beating the bushes for another project to take its place. As part of my search, I visited a former colleague who works at a small company in Southern California. This company designs a variety of products that utilize FPGAs exclusively (no ASICs), so I got a chance to understand a little bit more about the differences between ASIC and FPGA design. Here’s the follow-on then to my previous post An ASIC Guy Visits An FPGA World.

Recall that the first 4 observations from my previous visit to FPGA World were:

Observation #1 - FPGA people put their pants on one leg at a time, just like me.

Observation #2 - I thought that behavioral synthesis had died, but apparently it was just hibernating.

Observation #3 - Physical design of FPGAs is getting like ASICs.

Observation #4 - Verification of FPGAs is getting like ASICs.

Now for the new observations:

Observation #5 - Parts are damn cheap - According to the CTO of this company, Altera Cyclone parts can cost as little as $10-$20 each in sufficient quantities. A product that requires thousands or even tens of thousands will still cost less than a 90nm mask set. For many non-consumer products with quantities in this range, FPGAs are compelling from a cost standpoint.

True, the high-end parts can cost thousands or even tens of thousands each (e.g. for the latest Xilinx Virtex 6). But considering that a Virtex 6 part is 45nm and has the gate-count equivalent of almost 10M logic gates, what would an equivalent ASIC cost?

Observation # 6 - FPGA verification is different (at least for small to medium sized FPGAs) - Since it is so easy and fast and inexpensive (compared to ASIC) to synthesize and place and route an FPGA, much more of the functional verification is done in the lab on real hardware. Simulation is typically used to get a “warm and fuzzy” that the design is mostly functional, and then the rest is done in the lab with the actual FPGA. Tools like Xilinx ChipScope allow logic-analyzer-like access into the device, providing some, but not all, of the visibility that exists in a simulation. And once bugs are found, they can be fixed with an RTL change and reprogramming the FPGA.

One unique aspect of FPGA verification is that it can be done in phases or “spirals”. Perhaps only some of the requirements for the FPGA are complete or only part of the RTL is available. No problem. One can implement just that part of the design that is complete (for instance just the dataplane processing) and program the part. Since the same part can be used over and over, the cost to do this is basically $0. Once the rest of the RTL is available, the part can be reprogrammed again.

Observation # 7 - FPGA design tools are all free or dirt cheap - I think everybody knows this fact already, but it really hit home talking to this company. Almost all the tools they use for design are free or very inexpensive, yet the tools are more than capable to “get the job done”. In fact, the company probably could not operate in the black if they had to make the kind of investment that ASIC design tools require.

Observation # 8 - Many tools and methods common in the ASIC world are still uncommon in this FPGA world - For this company, there is no such thing as logical equivalence checking. Verification tools that perform formal verification of designs (formal proof), System-Verilog simulation, OVM, VMM…not used at all. Perhaps they’ll be used for the larger designs, but right now they are getting along fine without them.

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FPGA verification is clearly the area that is the most controversial. In one camp are the “old skool” FPGA designers that want to get the part in the lab as soon as possible and eschew simulation. In the other camp are the high-level verification proponents who espouse the merits of coverage-driven and metric-driven verification and recommend achieving complete coverage in simulation. I think it would really be fun to host a panel discussion with representatives from both camps and have them debate these points. I think we’d learn a lot.

Hmmm…

harry the ASIC guy

My morning routine is pretty, well, routine.

Get up.  Wake the kids.

Check email.  Ask the kids to stop jumping on the couch.

Check Twitter. Tell the kids again to stop jumping on the couch.

Check my Google Reader. Glare at the kids with that “I’ve asked you for the last time” look.

You get the idea.

This Wednesday morning, somewhere in between conversations with my kids, walking the dog, and getting ready for work, I came across the following comment on a friend’s blog:

Ron, we are listening.

http://www.mentor.com/blogs

Ron Fuller
Web Manager, Mentor Graphics

For background, Ron Ploof is the guy who got the crazy idea almost 3 years ago that Synopsys should be doing something in this new world called social media. (Actually, I don’t think the term “social media” had even been coined back then). He evangelized this belief to the VP of Marketing at Synopsys and created for himself a job as Synopsys’ “New Media Evangelist” (actual title on his business card). He launched Synopsys’ first foray into social media, including podcasts, videos, and most prominently, blogs.

Synopsys’ success motivated Cadence to follow suit (something confided to me by Cadence’s former community manager). And it seems, according to the comment on Ron’s blog, it also motivated Mentor’s move into social media.

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I wanted to find out more about the Mentor blogs and I was able to set up some time to talk over lunch with Sonia Harrison at Mentor (see her sing at the Denali DAC party) . Sonia had helped me set up my previous interview with Paul Hofstadler and had extended me an invitation to attend the Mentor User2User conference (which, unfortunately, I could not attend). As it turns out, Sonia was the absolutely right person to talk to.

Even though I had only now become aware of Mentor blogs, Mentor had evidently coordinated their launch with the launch of their new website several months ago. Sonia was quite humble, but it seems that she was the driving force behind the blogs and Mentor’s presence in other social media like Twitter. She had been watching what was going on for some time, hesitant to jump in without a good plan, and now was the time.

According to Sonia, Mentor’s motivation for doing the blogs was to extend into a new media their “thought leadership” in the industry, to draw customers in to their website, and to exchange information with customers. Interestingly, Mentor did not hire an outside social media consultant or community manager like Cadence had. Rather, the project was homegrown. Sonia recruited various technical experts and others as bloggers. She developed “common sense” social media guidelines to make sure bloggers were informed of and played by social media rules (e.g. no sensitive or proprietary information, be polite, respect copyrights, give attribution).

According to Sonia, “one of the more difficult things was to get people to commit to blogging regularly. Writing takes time, it’s almost a full time job.” Despite this additional work burden, Mentor has no plans to bring in professional journalists as bloggers like Richard Goering at Cadence. And it doesn’t seem they need to. Simon Favre received a blog of the week award from System Level Design a few weeks ago, so they are doing quite well on their own.

Sonia does not have any specific measurable goals (page views, subscribers, etc.), which I think is a mistake, especially when her upper management comes asking for evidence that these efforts are paying off. My friend Ron likes to tell me that social media is the most measurable media ever and it’s a shame not to use the data.

I started playing with the site later in the afternoon and noticed a few things. First, when I added a comment to one of the blogs without registering, it did not show up right away, nor did I get a message that the comment was being moderated. It did show up later in the day, but it would be nice to at least be told that it was “awaiting moderation”. Still better, why moderate or require registration at all? The likelihood of getting inappropriate comments from engineering professionals is very low, and they can always be removed if need be. Moderation of comments will also kill a hot topic in its tracks. I’ve personally had the experience of publishing a new blog post late at night and waking up to several comments, some addressing other comments. Had I moderated the blog, none of those comments would have even showed up until later in the day.

Second, there was no way to enter a URL or blog address when leaving a comment. It is pretty standard practice to have this feature to allow readers to “check out” the person leaving the comment. Hopefully thay can add this.

On the positive side, the most important feature of a blog is the content and the content looks very good, especially the PCB blogs. Also, there is apparently no internal review or censorship of blog posts, so bloggers have the freedom to write whatever they want, within the social media guidelines of course.

 __________

It’s been almost 3 years since Ron made his first pitch to his manager. Who would have thought that the Big 3 and many others would have adopted social media in such a short time. Meanwhile, my kids are still jumping on the couch.

GTG

harry the ASIC guy

I hear so often nowadays that FPGAs are the new ASICs. So I decided to take off half a day and attend a Synopsys FPGA Seminar just down the street from where I’m working (literally a 5 minute walk). I would like to share some observations as an ASIC guy amongst FPGA guys and gals.

Observation #1 - FPGA people put their pants on one leg at a time, just like me. (Actually, I sometimes do both legs at the same time, but that’s another story). I had been led to believe that there was some sort of secret cabal of FPGA people that all knew the magic language of FPGAs that nobody else knew. Not the case. Although there is certainly a unique set of terminology and acronyms in the FPGA arena (LUTs, DCM, Block RAM) they are all fairly straightforward once you know them.

Observation #2 - I thought that behavioral synthesis had died, but apparently it was just hibernating. There is behavioral synthesis capability in some of the higher-level FPGA tools. I’ve never used it, so I can’t say one way or the other. But it sure was a blast from the past (circa 2000). Memories of SPW, Behavioral Compiler, Cossap, Monet, Matisse.

Observation #3 - Physical design of FPGAs is getting like ASICs. There are floorplanning tools, tools that back-annotate placement back into synthesis, tools that perform synthesis and placement together, tools for doing pre-route and post-route timing analysis. Made me think of Floorplan Manager, Physical Compiler, and IC Compiler.

Observation #4 - Verification of FPGAs is getting like ASICs. It can take a day to resynthesize and route a large FPGA to get back in the lab debugging. That’s an unacceptable turnaround time for debugging an FPGA with lots of bugs. Assertions (SVA, PSL), high-level verification languages (System-Verilog / OVM / VMM) and cross domain checkers are methods being stolen from the ASIC design world to address large FPGA verification. The trick is deciding when there has been enough simulation to start debug in the lab.

After this session, I think this ASIC guy is going to feel right at home in the FPGA world of the future.

harry the ASIC guy

(Read Part II of this series here)

A colleague of mine, Alvin Cheung, recently interviewed Chris Schalick of GateRocket regarding his experiences in founding a high-tech startup company. That interview is reposted below by permission of both parties.

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Chris Schalick is VP of Engineering, CTO, and Founder of GateRocket, Inc. After working in the ASIC and FPGA industry for more than 15 years, Chris founded the company to solve one of the fundamental problems with FPGA design, the ability to simulate hardware FPGA behavior within the design verification environment. GateRocket partners with the three major Electronic Design Automation (EDA) providers, Mentor Graphics, Cadence, and Synopsys, to be able to “plug-in” their hardware to the software simulation environment.

Alvin Cheung is currently a CAD Manager in the aerospace industry. Previously, Alvin worked at TI, Artisan Components and other companies doing ASIC and library development.

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Alvin: Hi Chris. I want to start off by asking a couple of questions that are not necessarily related to FPGA technology but more towards a start-up company. I see that you founded the company in Oct. 2004. You were working for someone else before you decided to found your company. What made you want to start you own business?

Chris: Well, it is something that I always wanted to do as a kid. I love to build things. In the 15 years that I was an ASIC designer, I saw that when I went from ASIC to FPGA there were a lot of problems with debugging the FPGA. The parts that would work in simulation perfectly ended up not working in the lab at all. A lot of ASIC designers have the same issues going from ASIC to FPGA and there were not any tools out there to address this problem. I thought to myself, “There has to be a better way to do the debugging on the FPGAs.” That’s how I came up with the idea. I tested the idea with a couple of colleagues and founded the company. Our RocketDrive builds on the idea of using a logic analyzer in the lab and puts it at the finger tips of the designers doing functional verification with a simulator. You don’t have to reprogram the FPGA over and over again, troubleshoot, and recode your design.

Alvin: Did you find that you needed to adapt from your engineering skills to marketing or sales skills? Did you find that a challenge and a difficult transition?

Chris: In a small company you have to do a lot of things. In the beginning, I had to do everything from calling the customers, talking to the vendors, talking to partners and talking to investors. You’re right in that most engineers don’t have a lot of skills in those areas. I had to learn a lot by trial and error.

Alvin: Do you see a change in lifestyle since you started the company? Is it worthwhile?

Chris: I worked at several start-ups before starting GateRocket. I’m used to working long hours and with a small group of people. Over time, working focused hours with a small group can be more productive than larger groups with more resources. Our company has had its up and downs; keeping a positive attitude and going back to do the right thing is the most important thing.

Alvin: I see that you’ve secured your funding from venture and angel investors. Was it difficult to secure the Series A funding? Did the VC require you to change your plans? Were there a lot of obstacles?

Chris: Raising money is trial and error. The process is always lengthy but not necessarily an obstacle. There are always people who will say “No” and want you to address “one more” thing, but addressing it does not necessary mean that they’ll invest or that you will succeed. All you really need is the one “Yes” from the right guys and you can’t be concerned about the “No’s”. As far as the obstacles, they always want more data, analysis, financial projections and references. Those things are not unreasonable and you do your best to provide them with the information. When I put my own money on the line, I ask for the same things.

Alvin: How long did it take you to develop the “RocketDrive? Is it your first product?

Chris: Yes, the “RocketDrive” is our first product and our only product. It took me 18 months for the first prototype and since our first prototype we have dramatically enhanced the hardware. It took us 2 ½ years to ship our 1st production unit and we worked closely with our customers and partners to develop the product. We are in our 5th year and shipping units. We are constantly improving the product and continue development of RocketDrive as a platform and new software products that run on it. Stay tuned!

Alvin: What would you say are the top three skills needed to be a successful entrepreneur?

Chris: Hmm… I would say the ability to maintain focus. Things don’t always go the way you want. Many things that you don’t expect to happen will happen. You have to maintain focus and go back and look at problems from another angle. The second would be the ability to stay positive. You just keep your chin up and tell yourself you can do it. The third would be imagination. Sometimes the right answer is not obvious. There’s a saying that, “You have to think outside the box.” You really do to succeed. You need to see things from many different angles and sometimes the right answer is not the obvious one. Our first prototype was nothing like what we currently ship.

Alvin: What is your favorite aspect of being an entrepreneur?

Chris: You know the saying that, “You have to play big to win big.”? Well that’s true. From the creative aspect, I’ve always liked to build things and starting a company provides a unique chance to build things that you might not otherwise be able to. Of course money is also a big factor. Although there’s no guarantee of financial success, it certainly is a motivator. I would say it is the combination of the two.

Alvin: Was there a lot of trial and error with your product? Do you find yourself in situations where there is already a competitor out there that has similar technology? If yes, how did you differentiate them from your product?

Chris: There was a huge amount of trial and error. Success is always a trial. Sometimes the answers are not obvious. You have to be persistent and look outside the box. You keep looking for the solution until your find the answers. Our current model looks nothing like our original prototype on the inside. On the outside with the simulator, it looks the same. But on the inside, everything has changed. We believe we are the first product in the market that does logic simulation directly with the FPGA. So, no, there is no direct competition. There are alternatives to develop FPGAs – build a prototype, program the FPGA, take it to the lab, connect it to the logic analyzer and hope everything works according to what you simulate with your RTL and testbench. What we are doing is changing the design flow and people’s concept of verifying the design. You can debug your design on actual silicon before you take it to the lab.

Alvin: How is your company adjusting to the current economic downturn? Did you have to downsize or change your priorities to adjust?

Chris: The environment looks bad on the surface, but people are still working on FPGAs. Some people have fewer dollars to spend, but we are still getting positive feedback with our product and we are selling more of them. We certainly have lots of activity lately with our product due to the growing size and number of FPGA designs.

Alvin: Actually in the current economic climate, would people choose FPGA over ASIC?

Chris: Yes, you are right. With the cost of the ASIC process, more and more people are looking to see how they can fit their designs in FPGAs instead of ASICs. With FPGAs getting larger and design technology getting smaller, more and more designers are choosing FPGA for their designs.

Alvin: I’m going to ask my last question of the interview and don’t want to take too much of your time. So I’m going to end with asking, what is your next step? Where do you see the company going from here?

Chris: Though our company is still growing, we are looking for ways to become the household name when it comes to FPGA development. We are demo’ing to customers and showing them the actual behavior of the simulator on silicon. We are working to craft the message and to expand our presence in the market. We are developing our online presence. We are going to DVCon, FPGA summit, and DAC, and really our best marketing is from “word of mouth”. We want our customers to be successful and in turn we can become successful.

Alvin: Do you think you would IPO or get the company to be on a merger/acquisition deal anytime soon?

Chris: In this environment, I don’t think it is the right time for an IPO. We are focusing on our customers, enhancing the product and expanding our market presence.

Alvin: Ok. Well, thank you for letting me take a big chunk of your time from your busy schedule. Thank you so much for the interview.

Last night you may have watched the NBA Playoff game in which the Orlando Magic came back to defeat the heavily favored Cleveland Cavaliers. Great game!!!

Or the finale of American Idol in which Kris Allen came back to defeat the heavily favored Adam Lambert. Great show!!!

What did I do last night? I listened to the Q2 2009 Synopsys earnings call. Great conference call!!!

(OK … I’ll admit it wasn’t as exciting and nail biting as either of the other viewing options. Just think of it like this: I took on the work of listening to the call and summarizing it for you, in order to free you up to watch the game or idol. You can thank me later )

Here’s the summary. (You can read the full transcript here if you like).

Financials

On the up side, Synopsys had a good Q2, beating their revenue and earnings per share guidance slightly. On the down side, Synopsys lowered its revenue and cash flow guidance slightly for the rest of the year, allowing for potential customer bankruptcies, late payments, and reduced bookings. Customers are approaching Synopsys to “help them right now through this downturn”, i.e. to reduce their cost of software. It looks like the recession is finally catching up to them.

As I finish off this post on Thursday morning, it looks like the analysts agree. Synopsys shares are down 10%, so it seems they are getting punished for revising their forecast. 

Still, Synopsys is in very good financial health, with $877M in cash and short term investments. Their cash flow is going to go down the rest of the year, so they will eat into this fund, but they will still have plenty to selectively acquire strong technology that might add to their portfolio, as they did with the MIPs Analog Business Group.

Themes

There were 2 themes or phrases that kept recurring in the call that I am sure were points of emphasis for Aart.

First, the word “momentum” was used 6 times (by my count) during the call. Technology momentum. Customer momentum. Momentum in the company. Clearly, Synopsys is trying to portray an image of the company building up steam while the rest of the industry wallows in the recession.

Second, customers are “de-risking their supplier relationships”, i.e. looking to consolidate with an EDA vendor with strong financials who’ll still be there when the recession ends. Again, Synopsys is trying to portray itself as the safe choice for customers, hoping to woo customers away from less financially secure competitors like Cadence and Magma. This ties in with the flurry of “primary EDA vendor” relationships that Synopsys has announced recently.

The opportunity for Synopsys (and danger for the competition) is to pick up market share during this downturn and it looks like that may be happening as companies “de-risk” by going with the company with the “momentum” and a “extraordinarily strong position”. Or at least that’s the message that Synopsys is sending.

Technology

Aart did rattle off the usual laundry list of technology that he wanted to highlight, including some introduced last year (e.g. Z-route). Of note were the following:

• Multi-core technology in VCS with 2x speedup (is 2x a lot?)
• Custom Designer, which Aart called “a viable alternative to the incumbent” (ya know marketing didn’t pick the word “viable”)
• Analog IP via the MIPS Analog Business Group acquisition, especially highlighting how that complements the Custom Designer product (do I see “design kits” in the future?)
• The Lynx Design System (see my 5-part series)
• IC-Validator (smells like DRC fixing in IC Compiler - Webinar today, I’ll find out more)

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In summary, Synopsys had a good quarter, but they have finally acknowledged that they are not immune to the downturn and they expect to get impacted the next few quarters.

harry the ASIC guy

It was 1992 and I was supporting the Motorola Iridium project in Chandler, AZ. There was a project lead named Steve who I was tasked to work with. My job was to get certain elements of our DesignWare library working properly to support his ASIC design team.

Steve was a bit of a control freak. Whenever there were technical decisions to be made, Steve wanted to be the one making the decisions. And once he made his decision, there was no changing it. You see, Steve had a big ego and did not like to be wrong, much less wrong in front of his team.

Unfortunately, his decisions were not always the correct decisions and I had no problem telling him that. You see, I had a big ego too.

As you can imagine, Steve and I did not get along very well.

Fortunately, I had a boss who had dealt with Steve before and who gave me some advice that I carry to this day. He suggested that I bring the relevant facts to Steve and present them in such a way that the decision was obvious. Then, I needed to say these words, “I’m not sure what is the best choice. What do you think?”

As hard as it was for me to relinquish control of these decisions, it turned out to be the right way to handle Steve. Instead of feeling like he was put on the spot to win a debate with the local AE, he felt like a respected authority figure. With this pressure removed, Steve usually ended up making the right decision (i.e. the one I would have recommended).

Steve was happier. I was happier. And we got a lot more productive work done as a result!

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The soft skills that I describe in the story above do not come naturally to most engineers. A matter of fact, I’ve often heard it said “he’s a great engineer, but I’d never take him to a client”. So I was very interested when I came across a press release describing how Mentor Graphics and RTM Consulting collaborated to develop a soft skills training class for Mentor consultants. I sent an email to Paul Hofstadler, VP of Consulting at Mentor, requesting to talk to him about the class, and he graciously accepted.

According to Paul, Mentor’s Services are typically focused on deploying to their clients new working processes around the EDA tools that Mentor sells. That is, they are teaching their clients to fish, rather than selling them fish. As you can imagine, it requires a great deal of influence and political savvy to effectively implement these types of changes in a client’s organization. Unfortunately, these skills don’t necessarily come naturally for most engineers. Indeed, when Mentor went back and examined the projects that had challenges, they discovered that the core issues were not technical, but rather involved corporate politics and communication issues.

Paul decided that he needed to increase the soft skills of his consultants in order to be more effective on projects and to recognize opportunities for more business in a tough economy. “More than half the work in consulting is finding and growing people”.  Rather than building a training program internally, or piecing one together from existing off-the-shelf classes, Paul engaged with RTM Consulting to develop a customized class to meet Mentor’s specific needs. “We didn’t want to pull our best consultants off of time critical customer projects to develop the class. They are the ones guiding our customers through complex projects. In addition, we wanted the outside point of view that RTM brought to the situation.”

Most of the course material came from RTM Consulting . The specific case studies and industry specific material came from Mentor. Paul had senior consultants help with the development of the material, especially the case studies which were based on real experiences. The result is a 3 day course that is very hands-on. There is standard lecture time and also several 5-6 person role play case studies. “The collaboration with Mentor Graphics was key to honing in on customization of the training to give the them the best chance at gaining the right skills necessary, and providing a solid return on their educational investment”, according to Randy Mysliviec, CEO of RTM Consulting.

Paul Hofstadler particularly praised the case studies. “The case studies were the most interesting part of the course. I never knew what was going to come out of them. Each group solved the case studies slightly differently using the skills taught in the class.” Even so, Paul resisted the urge to let the consultants bring real customer situations into the class for fear that the entire class would end up working on one real customer case. Instead, Mentor asked consultants to present real case studies after the class, several weeks later, and present them to the internal team. This served as a reinforcement of the material and helped to put the course material into practice.

A 3-day training course for the entire consulting team seems like a big investment. “Ironically, the cost of soft skills training can often be offset by just a single large project overrun or a collection of overruns”, according to Randy Mysliviec. Fortunately, the timing of the class coincided with an end of year lull in delivery, so Mentor was able to implement the training class with minimal customer project impact as well.

Since the training was administered just a few months ago, it is difficult to definitively measure the value. However, there is strong anecdotal evidence that it is working. One senior consultant, who was very skeptical at the beginning, used the techniques in the class to turn around a difficult customer (similar to my story at the beginning of this post). Paul has indicated that “consulting orders this quarter are a lot better than last quarter” and he attributes that in part to the training, particularly the parts that help consultants recognize potential follow-on opportunities for more business.

“In this economy, it is more important than ever to understand the customer’s needs, communicate effectively, and deliver excellent solutions on every engagement” said Paul in summary. “It is clear to me that our projects are running more smoothly after the training. As a bonus, our repeat customer order rate is up indicating that we are continuing to deliver high value to our customers despite the ‘interesting’ times in which we find ourselves.”

Due to the success of the training, Mentor is looking at extending the training to other parts of the consulting organization and to other organizations in Mentor. In the meantime, RTM Consulting is offering the course for other customers, minus the Mentor specific material, of course. “The soft skills needs at Mentor are certainly not unique in the professional and consulting services world”, says’ Randy Mysliviec. “Most technology and pure services companies do a good job of teaching their teams about products, services, and technologies they need to know to effectively serve clients. What is most often missed are the soft skills necessary for consultants to effectively interact with their clients.”

Thanks to folks like RTM Consulting, these soft skill aren’t hard to learn after all.

harry the ASIC guy

I recall taking a course called The Counselor Salesperson when I was an AE at Synopsys. The course was very popular across the industry and was the basis for the book Win-Win Selling. It advocated a consultative approach to sales, one in which the salesperson tries to understand the customer’s problem first and provide a solution that he needs second. Sounds obvious, but how often do you encounter a salesperson who knows he has what you need and then tries to convince you that you have a problem?

One of the techniques in the process is called the “Magic Wand” wherein the salesperson asks the customer “What would it be like if …”. This open-ended type of question is designed to free the customer’s mind to imagine solutions that he’d otherwise not consider due to real or imagined constraints. That’s the type of question I asked last week when I asked: What would you do with 1000 CPU’s? And boy did it free your minds!

Before I go into the responses, you may be wondering what was my point in asking the question in the first place.  Well, not so surprisingly, I’m looking to understand better the possible applications of cloud computing to EDA and ASIC design. If a designer, design team, or company can affordably access a large number of CPUs for a short period of time, as needed, what would that mean? What would they be able to do with this magic wand that they would not even have thought of otherwise?

I received 8 separate responses, some of them dripping with humor, sarcasm, and even disdain. Good stuff! I’ve looked them over and noticed that they seem to fall into 4 groups, each of which highlights a different aspect or issue of this question.

“Rent Them Out”

Gabe Moretti had the best response along these lines, “(I’d) heat my house and pool while selling time to shivering engineers”. Jeremy Ralph of PDTi put some dollar value on the proposition, calculating that he could make $8.25M per month sub-licensing the licenses and CPUs. While Guarav Jalan pointed out that I’d need to also provide bandwidth to support this “pay-as-you-use” batch farm.

The opportunity is to aggregate users together to share hardware and software resources. If I buy a large quantity of hardware and software on a long-term basis at discounted rates, then I can rent it out on a shorter-term basis at higher rates and make money. The EDA company wins because they get a big sale at a low cost-of-sales. The customers win because they get access to tools on a pay-as-you-go basis at lower cost without a long-term commitment. And I win because I get to pocket the difference for taking the risk.

“Philanthropy”

One of the reasons that Karen Bartleson and I get along so well is that we’ve both been around the EDA industry for some time (we’ll leave it at that). As a result, we not only feel connected to the industry, but also some sense of responsibility to give back. Karen would train university student’s on designing SOCs. I’d train displaced workers on tools that can help them find a new job.

Even though this is not really a business model, I think it is still something that the EDA vendors should consider. Mentor is already very active in promoting it’s Displaced Worker Program. Autodesk and SolidWorks are giving away free licenses to the unemployed. This type of program should be universal. Using cloud computing resources is an easy way to make it happen without investing in lots of hardware.

(On a side note: PLEASE, PLEASE encourage anyone you know at Synopsys and Cadence to follow Mentor’s lead. Synopsys did this in 2001 and Cadence once had a “Retool-To-Work” program that was similar. I truly believe that both companies have that same sense of corporate responsibility as Mentor has, but for some reason they have not felt the urgency of the current situation. I am personally going to issue a daily challenge on Twitter to Synopsys and Cadence to follow suit until it happens. Please Retweet.)

“Do Nothing”

John Eaton pointed out that it is very difficult to use any additional capability offered as “pumpkinware” if you know it will evaporate within a month. It would take that long to set up a way to use it. And John McGehee stated that his client already has all the “beer, wine, and sangria” they can drink (New Yorkers - do you remember Beefsteak Charlie’s?), so he’d pass. John: Can you hook me up with your client ?

Seriously,  it certainly requires some planning to to take advantage of this type of horsepower. You don’t just fire off more simulations or synthesis runs or place and route jobs without a plan. For design teams that might have access to this type of capability, it’s important to figure out ahead of time how you will use it and for how long you will need it. If you will be running more sims, which sims will they be? How will you randomize them? How will you target them to the most risky parts of the design?

“Run Lots of Experiments”

Which brings us to Jeremy Ralph’s 2nd response. This one wins the prize as best response because it was well thought out and also addressed the intention of the magic wand question: what problem could you solve that you otherwise could not have solved? Jeremy would use the resources to explore many different candidate architectures for his IP (aka chiplet) and select the best one.

One of the key benefits of the cloud is that anyone can have affordable access to 1000 CPUs if they want it. If that is the case, what sorts of new approaches could be implemented by the EDA tools in addressing design challenges? Could we implement place and route on 1000 CPUs and have it finish in an hour on a 100M gate design? Could we partition formal verification problems into smaller problems and solve what was formerly the unsolvable? Could we run lots more simulations to find the one key bug that will kill our chip? The cloud opens up a whole new set of possibilities.

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I’ve learned a lot from your responses. Some were expected and some were not. That’s what’s fun about doing this type of research … finding the unexpected. I’ll definitely give it some thought.

harry the ASIC guy