Posts Tagged ‘SoC’

Hot Topics from SNUG San Jose 2008 - Day 1 AM

Monday, March 31st, 2008

I just attended Aart DeGeus’ keynote address at SNUG 2008 and there were two highlights:

  1. Synopsys is back in the analog design market! Filling the gap in their product portfolio, they announced a new in-house developed product called Orion that is aiming directly at the Cadence users of Virtuoso. Orion is in beta right now and will work with Open Access. They did a canned demo and highlighted ease-of-use and productivity over Virtuoso.
  2. Besides questions on Orion, all the other questions were regarding VMM / OVM and the path to getting a truly open standard verification methodology. Cliff Cummings and John Cooley asked the most direct questions on this topic, such as:
  • Will VMM ever be truly open and not just licensed?
  • Is there any attempt to speak directly to Mentor and Cadence to try to combine OVM and VMM?
  • Can we use VMM with another System Verilog simulator?

Synopsys’ plan is to donate VMM to Accellera and have Accellera drive a standard verification methodology. When asked about working with Mentor/Cadence, Synopsys asked the designers to try to push them to the table within Accellera. I expect this battle will continue.

More later…. harry the ASIC guy

What the heck am I getting myself into???

Sunday, March 30th, 2008

As a veteran ASIC designer … EDA applications engineer … consultant … project manager … biz dev manager … I’ve played a variety of key roles in the development of dozens of complex ASICs and SoCs. I’ve seen the industry from many perspectives … technical, managerial, financial … and I’ve seen what it takes to be successful and how little it takes to fail.

But, what fascinates me the most is the people. It’s the reason I left a desk job doing hands-on design at TRW to become an applications engineer at Synopsys working with people. And with the advent of new internet technologies (Open Source, Web2.0 …) the people are becoming even more important as they find new ways to work together and support each other. And turn the industry on it’s head.

Still, I don’t hear much about the people aspects of ASIC design from EDA vendors or trade publications … it doesn’t sell tools or subscriptions. And I don’t read much from the other industry blogs, many of them excellent for sure, as they focus more narrowly on rapidly evolving EDA technologies like verification.

For this reason, I started … to share my insights into the people aspects of ASIC engineering for those who, like me, feel they are under-valued. I hope you find these insights to be thought-provoking and of practical value and I welcome your insights and comments. After all, several thousand heads are better than one :-)

harry the ASIC guy