harry … the ASIC guy

One of the shortest but most relevant exchanges during the Cadence analyst call concerning the Mentor acquisition was an exchange between Sterling Autry of JP Morgan and Kevin Palatnik, CFO of Cadence.

About 27 minutes into the conference call, Sterling Autry asked why Cadence was estimating only $50M in operating income benefit considering Mentor’s operating income in 2007 was $120M. Indeed, $1.6B to acquire $50M in income seems like a poor deal indeed.

Kevin Palatnik’s response included the following, “the industry has had a history, from a customer perspective, of trying to get more and include features and not pay for it. So I think we just have to be able to demonstrate value to the customers. So I think, in the short term, I think, there is always the customers asking for the combination and not paying for it.”

The crux of the issue is simple math: 1 + 1 = ??? …how much will Cadence-Mentor be able to charge for their combined products?  If  1+1 > 1.5, then the combined company will be in pretty good shape.  If 1 + 1 < 1.5, then it will be difficult to “extract the value” of the acquisition. In that case, expect lots of layoffs, products being scrapped, and products being sold off.

From my experience, Kevin Palatnik is only partially correct that “the industry has had a history, from a customer perspective, of trying to get more and include features and not pay for it”. When I started with Synopsys in 1992, their flagship tool was Design Compiler. Synopsys added new features and voila…DC-Expert.  Then DC-Ultra. Now DC-Graphical. Each one sold at a premium to the predecessor and customers would pay for the upgrades.

But not without voicing their displeasure, both privately and also publicly on places like ESNUG. It often seemed arbitrary and self-serving to customers what Synopsys deemed an “update” (covered by their tool support) and what they deemed an “upgrade”.  And they felt they were being nickel-and-dimed.

On the other hand, people need to eat, and the EDA tool developers are no exception. They do not work for free. It seems unique to the EDA industry, that customers expect, once they buy a tool, to get any and all improvements to the product for free. This is not the case when I buy MS Office or most any other desktop application, but it is definitely a reality in EDA.

To add to the confusion, I can now download almost any desktop application I need for free as open-source (e.g. Open Office), or use it for free online (e.g. Google Docs), and get access to upgrades for free as well. This has changed customer expectations dramatically.

I’d like to know what you (EDA vendors and customers) think about this:

1. Should customers pay more for EDA tool enhancements or should they be part of the tool “support”?
2. How do you decide what is an “update” and what is an “upgrade”?

harry the ASIC guy

OK … I’m registered to go to DAC for at least one day, maybe two. I’ll definitely be there on Tuesday and probably Wednesday evening for a Blogging “Birds-of-a-Feather” session that JL Gray is setting up. Besides hitting the forums and other activities, I’ll have about half a day to attack the exhibit floor or the “suites” to look at some new technology. If you want to meet up, drop me an email and we can arrange something.

Cadence won’t be there and I already talk to Synopsys and Mentor on a regular basis, so I’m planning on focusing on smaller companies with new technology. Here’s what’s on my list so far…

Nusym - They have some new “Path Tracing” technology that finds correlations between a constrained random testbench and hard-to-hit functional coverage points. With this knowledge, they claim to be able to modify the constraints to guide the simulation to hit the coverage points. The main benefit is in getting that last few % of functional coverage that can be difficult with unguided constrained random patterns.

Chip Estimate - Having been around for a few years and recently bought by Cadence, they are basically a portal where you can access 3rd party IP and use the information to do a rough chip floorplan. This allows you to estimate area, power, yield, etc. I’m real curious as to their business model and why Cadence bought them. At a minimum, it should be entertaining to see the hyper-competitive IP vendors present back-to-back at half hour intervals on the DAC floor.

I have a few others on my list, but there are so many small companies that it’s hard to go thru them all and decide what to see. That’s where I need your help.

What would you recommend seeing and why?

On her Standards Game Blog  today, Karen Bartleson announced that Accellera is forming a subcommittee to define a standard for verification interoperability.  That is, to try to settle the VMM / OVM war.  As I have stated before in comments on JL Gray’s Cool Veification Blog, this is the right move because it give us input into the process, rather than just the EDA vendors controlling the process for their own benefit.  Also, as I argued in a previous post entitled “The Revolution Will Not Be Televised”, the influence and pressure of the verification community and especially the Cool Verification Blog were at least in part responsible.

Of course, Synopsys will tell you that they are just doing the right thing

It’s not clear how Cadence and Mentor will respond.  Hopefully they’ll join the effort.  Let’s keep the pressure on.

My friend Ron has a knack for recognizing revolutionary technologies before most of us. He was one of the first to appreciate the power of the browser and how it would transform the internet, previously used only by engineers and scientists. He was one of the first and best podcasters. And now he’s become a self-proclaimed New Media Evangelist, preaching the good news of Web 2.0 and making it accessible to “the rest of us”.

Most of us are familiar with mainstream Web 2.0 applications, whether we use them or our friends use them or our kids use them. Social and professional networks such as My Space, Facebook, and LinkedIn. Podcasts in iTunes. Blogging sites on every topic. Virtual worlds such as Second Life. Collaboration tools such as Wikipedia. File sharing sites such as Youtube and Flickr. Social bookmarking sites such as Digg and Technorati. Open source publishing tools such as Wordpress and Joomla. Using these technologies we’re having conversations, collaborating, and getting smarter in ways that were unimaginable just 5 years ago. Imagine, a rock climber in Oregon can share climbing techniques with a fellow climber in Alice Springs. And mostly for free, save for the cost of the internet connection.

When we think of Web 2.0, we tend to think of teenagers and young adults. But this technology was invented by us geeks and so it’s no surprise that the ASIC design world is also getting on-board. Here are some examples from the ASIC Design industry:

• Open Cores Design IP
• Cool Verification Blog
• DFT Digest
• ASIC / SoC Design Blog
• Verification Guild Forums
• LinkedIn / Yahoo group on ASIC Design
• OPML file that lists more blog feeds related to ASIC Design.

Social media is networking ASIC designer to ASIC designer enabling us to be smarter faster. But that’s not all. Many forward looking companies have recognized the opportunity to talk to their customers directly. About 6 months ago, Synopsys launched several blogs on its microsite. Xilinx also has a User Community and a blog. It’s great that this is happening, but does it really make much of a difference? Consider what I believe could be a watershed event:

A few months ago, JL Grey published a post on his Cool Verification blog entitled The Brewing Standards War - Verification Methodology. As expected, verification engineers chimed in and expressed their ardent opinions and viewpoints. What came next was not expected … stakeholders from Synopsys and Mentor joined the conversation. The chief VMM developer from Synopsys, Janick Bergeron, put forth information to refute certain statements that he felt were erroneous. A marketing manager from Mentor, Dennis Brophy, offered his views on why OVM was open and VMM was not. And Karen Bartleson, who participates in several standards committees for Synopsys, disclosed Synopsys’ plan to encourage a single standard by donating VMM to Accellera.

From what I’ve heard, this was one of the most viewed ASIC related blog postings ever (JL: Do you have any stats you can share?). But did it make a difference in changing the behavior of any of the protagonists? I think it did and here is why:

• This week at the Synopsys Users Group meeting in San Jose, the VMM / OVM issues were the main topic of questioning for CEO Aart DeGeus after his keynote address. And the questions picked up where they left off in the blog post…Will VMM ever be open and not just licensed? Is Synopsys trying to talk to Mentor and Cadence directly? If we have access to VMM, can we run it on other simulators besides VCS?
• Speaking to several Synopsoids afterwards, I discovered that the verification marketing manager referenced this particular Cool Verification blog posting in an email to an internal Synopsys verification mailing list. It seems he approved of some of the comments and wanted to make others in Synopsys aware of these customer views. Evidently he sees these opinions as valuable and valid. Good for him.
• Speaking to some at Synopsys who have a say in the future of VMM, I believe that Synopsys’ decision to donate VMM to Accellera has been influenced and pressured, at least in part, by the opinions expressed in the blog posting and the subsequent comments. Good for us.

I’d like to believe that the EDA companies and other suppliers are coming to recognize what mainstream companies have recognized … that the battle for customers is decreasingly being fought with advertisements, press releases, glossy brochures, and animated Power Point product pitches. Instead, as my friend Ron has pointed out, I am able to talk to “passionate content creators who know more about designing chips than any reporter could ever learn”, and find out what they think. Consider these paraphrased excerpts of the cluetrain manifesto : the end of business as usual:

• The Internet is enabling conversations among human beings that were simply not possible in the era of mass media. As a result, markets are getting smarter, more informed, more organized.
• People in networked markets have figured out that they get far better information and support from one another than from vendors.
• There are no secrets. The networked market knows more than companies do about their own products. And whether the news is good or bad, they tell everyone.
• Companies that don’t realize their markets are now networked person-to-person, getting smarter as a result and deeply joined in conversation are missing their best opportunity.
• Companies can now communicate with their markets directly. If they blow it, it could be their last chance.

In short, this ASIC revolution will not be televised!!!

harry the ASIC guy

I just attended Aart DeGeus’ keynote address at SNUG 2008 and there were two highlights:

1. Synopsys is back in the analog design market! Filling the gap in their product portfolio, they announced a new in-house developed product called Orion that is aiming directly at the Cadence users of Virtuoso. Orion is in beta right now and will work with Open Access. They did a canned demo and highlighted ease-of-use and productivity over Virtuoso.
2. Besides questions on Orion, all the other questions were regarding VMM / OVM and the path to getting a truly open standard verification methodology. Cliff Cummings and John Cooley asked the most direct questions on this topic, such as:

• Will VMM ever be truly open and not just licensed?
• Is there any attempt to speak directly to Mentor and Cadence to try to combine OVM and VMM?
• Can we use VMM with another System Verilog simulator?

Synopsys’ plan is to donate VMM to Accellera and have Accellera drive a standard verification methodology. When asked about working with Mentor/Cadence, Synopsys asked the designers to try to push them to the table within Accellera. I expect this battle will continue.

More later…. harry the ASIC guy

As a veteran ASIC designer … EDA applications engineer … consultant … project manager … biz dev manager … I’ve played a variety of key roles in the development of dozens of complex ASICs and SoCs. I’ve seen the industry from many perspectives … technical, managerial, financial … and I’ve seen what it takes to be successful and how little it takes to fail.

But, what fascinates me the most is the people. It’s the reason I left a desk job doing hands-on design at TRW to become an applications engineer at Synopsys working with people. And with the advent of new internet technologies (Open Source, Web2.0 …) the people are becoming even more important as they find new ways to work together and support each other. And turn the industry on it’s head.

Still, I don’t hear much about the people aspects of ASIC design from EDA vendors or trade publications … it doesn’t sell tools or subscriptions. And I don’t read much from the other industry blogs, many of them excellent for sure, as they focus more narrowly on rapidly evolving EDA technologies like verification.

For this reason, I started theASICguy.com … to share my insights into the people aspects of ASIC engineering for those who, like me, feel they are under-valued. I hope you find these insights to be thought-provoking and of practical value and I welcome your insights and comments. After all, several thousand heads are better than one

harry the ASIC guy