harry … the ASIC guy

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What’s a blog without some sort of obligatory year end TOP 10 list?

So, without further ado, here is my list of the TOP 10 events, happenings, occurrences, observations that I will remember from 2009. This is my list, from my perspective, of what I will remember. Here goes:

1. Verification Survey - Last February, as DVCon was approaching, I thought it would be interesting to post a quickie survey to see what verification languages and methodologies were being used. Naively, I did not realize to what extent the fans of the various camps would go to rig the results in their favor. Nonetheless, the results ended up very interesting and I learned a valuable lesson on how NOT to do a survery.
2. DVCon SaaS and Cloud Computing EDA Roundtable - One of the highlights of the year was definitely the impromptu panel that I assembled during DVCon to discuss Software-as-a-Service and Cloud Computing for EDA tools. My thanks to the panel guests, James Colgan (CEO @ Xuropa), Jean Brouwers (Consultant to Xuropa),  Susan Peterson (Verification IP Marketing Manager @ Cadence), Jeremy Ralph (CEO @ PDTi), Bill Alexander (VP Marketing @ Blue Pearl Software), Bill Guthrie (VP Marketing @ Numetrics). Unfortunately, the audio recording of the event was not of high enough quality to post, but you can read about it from others at the following locations:
   

   > 3 separate blog posts from Joe Hupcey (1, 2, 3)

   > A nice mention from Peggy Aycinena

   > Numerous other articles and blog posts throughout the year that were set in motion, to some extent, by this roundtable

3. Predictions to the contrary, Magma is NOT dead. Cadence was NOT sold. Oh, and EDA is NOT dead either.
4. John Cooley IS Dead - OK, he’s NOT really dead. But this year was certainly a turning point for his influence in the EDA space. It started off with John’s desperate attempt at a Conversation Central session at DAC to tell bloggers that their blog sucks and convince them to just send him their thoughts. For those who took John up on his offer by sending their thoughts, they would have waited 4 months to see them finally posted by John in his December DAC Trip report. I had a good discussion on this topic with John earlier this year, which he asked me to keep “off the record”. Let’s just say, he just doesn’t get it and doesn’t want to get it.
5. The Rise of the EDA Bloggers.
6. FPGA Taking Center Stage - It started back in March when Gartner issued a report stated that there were 30 FPGA design starts for every ASIC start. That number seemed very high to me and to others, but that did not stop this 30:1 ratio from being quoted as fact in all sorts of FPGA marketing materials throughout the year. On the technical side, it was a year where the issues of verification of large FPGAs came front-and-center and where a lot of ASIC people started transitioning to FPGA.
7. Engineers Looking For Work - This was one of the more unfortunate trends that I will remember from 2009 and hopefully 2010 will be better. Personally, I had difficulty finding work between projects. DAC this year seemed to be as much about finding work as finding tools. A good friend of mine spent about 4 months looking for work until he finally accepted a job at 30% less pay and with a 1.5 hour commute because he “has to pay the bills”. A lot of my former EDA sales and AE colleagues have been laid off. Some have been looking for the right position for over a year. Let’s hope 2010 is a better year.
8. SaaS and Cloud Computing for EDA - A former colleague of mine, now a VP of Sales at one of the small but growing EDA companies, came up to me in the bar during DAC one evening and stammered some thoughts regarding my predictions of SaaS and Cloud Computing for EDA. “It will never happen”. He may be right and I may be a bit biased, but this year I think we started to see some of the beginnings of these technologies moving into EDA. On a personal note, I’m involved in one of those efforts at Xuropa. Look for more developments in 2010.
9. Talk of New EDA Business Models - For years, EDA has bemoaned the fact that the EDA industry captures so little of the value ($5B) of the much larger semiconductor industry ($250B) that it enables. At the DAC Keynote, Fu-Chieh Hsu of TSMC tried to convince everyone that the solution for EDA is to become part of some large TSMC ecosystem in which TSMC would reward the EDA industry like some sort of charitable tax deduction. Others talked about EDA companies having more skin in the game with their customers and being compensated based on their ultimate product success. And of course there is the SaaS business model I’ve been talking about. We’ll see if 2010 brings any of these to fruition.
10. The People I Got to Meet and the People Who Wanted to Meet Me- One of the great things about having a blog is that I got to meet so many interesting people that I would never have had an opportunity to even talk to. I’ve had the opportunity to talk with executives at Synopsys, Cadence, Mentor, Springsoft, GateRocket, Oasys, Numetrics, and a dozen other EDA companies. I’ve even had the chance to interview some of them. And all the fellow bloggers I’ve met and now realize how much they know. On the flip side, I’ve been approached by PR people, both independent and in-house. I was interviewed 3 separate times, once by email by Rick Jamison, once by Skype by Liz Massingill, and once live by Dee McCrorey. EETimes added my blog as a Trusted Source. For those who say that social media brings people together, I can certainly vouch for that.

harry the ASIC guy

I was contacted a few weeks ago by Synopsys’ PR agency to see if I’d be interested in covering an upcoming product announcement. I usually ignore these “opportunities” since the information provided is usually carefully wordsmithed marketing gobbledygook and not enough for me to really form an opinion. However, it turned out that this announcement was on a subject I know a little bit about, so I took them up on their offer.

The announcement was “embargoed“, that is, I was not to make it public until today. Embargoes are a vestige of the days when traditional journalism ruled the roost and when PR departments thought they could control the timing of their message. I don’t think embargoes benefit companies anymore since news is reported at light speed (literally) and people will write what they want when they want. Still, I consider it a sort of gentleman’s agreement so I’m not writing about it until today.

I also waited a little bit until the “mainstream press” wrote their articles. That let’s me point you to the best of them and conserve the space here for my own views, rather that regurgitating the press release and nuts and bolts.

(Update: Here is a very good description of the Synphony flow from Ron Wilson).

Today, Synopsys announced a new product called Synphony High Level Synthesis. You can read about this here. Basically, Synopsys is introducing a high level synthesis (aka behavioral synthesis) product that takes as its input Matlab M-Code and produces RTL Code, a cycle accurate C-model, and a testbench for simulation. Since I have not used the tool, I cannot comment on the capabilities or the quality of results or compare it to other tools on the market. However, I have had some past experience with tools like Matlab (specifically SPW) and Synphony (specifically Behavioral Compiler). So, here are my thoughts, observations, opinions that come to mind.

1. Synopsys, once the leader in behavioral synthesis, is now the follower - When Synopsys introduced Behavioral Compiler over a decade ago they were the first to preach the gospel of high-level synthesis and all the associated benefits. Architectural optimization. Faster simulation. Bridging the gap between system design and ASIC design. Smaller and easier to understand code. Dogs and cats living together. The promises never fully materialized and Synopsys seemingly moved out of the market. Meanwhile, Mentor introduced Catapult C, Cadence introduced C-to-Silicon, and several others including Forte, Agility, Bluespec, Synfora, ChipVision, and AutoESL introduced their own high-level synthesis tools. Now, after acquiring Synplify DSP through Synplicity, Synopsys is finally re-entering the market (at least for ASIC design) with Synphony. The hunted have become the hunters.
2. Synphony takes M-code from Matlab as its only source - Whereas most (but not all) other high-level synthesis tools input C like languages, Synopsys has chosen to input M-code only, at least for now. According to Chris Eddington, who is Director of Product Marketing for System-Level Products at Synopsys (according to his LinkedIn profile), approximately 60% of those who say they do “high-level design” are using M-code or some form of C (ANSI C, C++, System-C) for some portion of their design activities. Of those, slightly more use the C variants than M-code, which means that somewhere close to 25% of all ASIC designers could be a possible market for this tool.
3. Synopsys can try to leverage the Matlab installed base - As mentioned above, Synopsys estimates that 25% of high-level designers could use the Synphony tool which is a pretty big market. By targeting mainly algorithmic design, not control logic, Synopsys can try to serve the Matlab installed base with a more narrowly targeted offering which should make it easier to support. It also allows Synopsys to avoid a bloody battle over C dominance and to pursue a blue ocean strategy with Matlab’s installed base. Interestingly though, there is no partnership with MathWorks implied by this announcement.
4. Synphony leverages existing IP libraries - Libraries already exist for many common functions that were available for the Synplify DSP tool. The library elements are available as well for Synphony, allowing the designer to specify his functionality using this library or using M-code as the source.
5. An FPGA tool is being adapted for ASIC - This is probably one of the first times that a tool initially developed for FPGAs (Synplify DSP) is being adapted for ASICs. It’s usually the other way around (e.g. FPGA Compiler grew out of Design Compiler). It should be interesting to see if the FPGA tool can “cut-it” in the ASIC world.
6. Ties to implementation are seemingly tenuous - A tool that can take M-code as its input and produce RTL and C and do all the other things is all fine and good. But for Synphony to become more than an experimentation tool, it has to produce results (speed, area, power) as good or better than hand-coded RTL. However, the ties to the implementation tool (Design Compiler) are not as direct as even Behavioral Compiler was a decade ago. It seems that Synphony takes an approach where it pre-compiles and estimates timing for various blocks (kind of like building DesignWare libraries), but it assembles the design outside of DesignCompiler without all the associated timing views and engines necessary for true design and timing closure. It’s hard to understand how this can reliably produce results that consistently meet timing, but perhaps there is something that I am not aware of?
7. Focus on “algorithmic design”, not control - As mentioned above, Synopsys is going after the folks using Matlab. And those designers are developing algorithms, not state machines. In essence, Synphony can focus on the fairly straightforward problem of scheduling mathematical operations to hit throughput and latency goals and not deal with more complex control logic. Much simpler.
8. Conversion from Floating Point to Fixed Point - Anyone who has designed a filter or any DSP function knows that the devil is in the details, specifically the details of fixed point bit width. One choice of bit width affects downstream choices. You have to decide whether to round or truncate and these decisions can introduce unexpected artifacts into your signal. Synphony converts the floating point Matlab model into a fixed point implementation. Supposedly, it then allows you to easily fiddle with the bit widths to tweak the performance. Some earlier Synopsys products did this (Cossap, System Studio) and it’s a nice feature that can save time. We’ll see how useful it really is over time.
9. Synphony produces real RTL, as well as C-code and a testbench - One of the drawbacks of Behavioral Compiler is that it never produced a human readable form of RTL code. This made it hard to simulate and debug the RTL. Synphony supplies readable RTL (or so I am told) as well as cycle accurate C-code for system simulation and a testbench for block simulation. This should help facilitate full chip simulations for chip integration, since Synphony will probably only be used on blocks, not entire chips.
10. Couldn’t Synopsys come up with a better reference than Toyon Research Corporation - No offense to Toyon, but they are hardly a household name. It makes me wonder how many partners Synopsys has engaged in this development and how well tested this flow is. Not saying it isn’t well tested, just that Synopsys is making me wonder. Gimme a name I’ve heard of, please.

Only time will tell if Synphony is truly music to our ears, or if it is just SYNthesis that is PHONY.

harry the ASIC guy

As a kid, I always dreamed of being interviewed after hitting the game winning homerun or jump shot or throwing the game winning touchdown pass. Well, at this point in my life, the likelihood of those dreams is pretty much zilch. But, fortunately, I’ve been able to achieve something almost as great. A one-hour interview on Dee McCrorey’s Big Dreamers! The Reinvent Success Show.

So, after a full weekend of watching college football and then NFL football, and listening to those other guys getting interviewed after the game winning touchdowns, you can sit down at 6pm PDT, and unwind as Dee McCrorey, Risk Guru, Innovation Catalyst, and Business Coach asks me about my career from no-name engineer to “Harry the ASIC Guy”. You can always listen to the recording afterward if the time is inconvenient, but if you tune in live you can actually call into the show and ask questions, make comments, remind me of the $10 I borrowed for lunch and never gave back, whatever.

Honestly, I’m both flattered and embarrassed to have this opportunity. I met Dee just this past July at DAC in the Synopsys Conversation Central booth and we hit it off right away. Even after the sessions were over, Dee stayed and continued to ask questions trying to dig deeper and get at the core the topics we were discussing. She really has a desire to get to the essence of things which is a great asset for an interviewer, so I’m looking forward to some tough questions. She also has a thriving consulting business helping professionals reinvent their careers, both within corporations and individually, so I’m looking forward to working with her professionally as well.

For more information on the show, you can go here. I hope you can join me.

harry the ASIC guy

Our summer has been pretty hectic and full of uncertainty, so we put off planning a short vacation until just this past weekend. We usually go up to Big Bear and stay at this one place that is dog friendly and has a pool for the kids and is close to town. We’ve stayed there 3 times before and have always been very happy.

This past Saturday morning, I Googled the name of the resort in order to get the web address when I noticed that there was a Trip Advisor listing for the place. So, I thought I’d check it out. Much to my surprise there was a slew of negative reviews. I dug a little further and found that many of these reviews were placed around the same date (since we had been there last) by people who only rated this one place and who had very similar complaints. These reviews seemed suspicious, but who knew, maybe some had merit. These could be legit or they could be someone posting them on the behalf of competing resorts to discredit their competitor.

As I surfed a little more, I found comments on some other pages indicating that this sort of negative posting on rating sites had become epidemic for Big Bear. Who knew that the lodging industry in this cozy little town in the mountains was so cutthroat? It’s a good example of a lose-lose strategy. Now I can’t trust any of the ratings!

In the end we ended up booking at a different resort, mostly due to other factors, but admittedly also due in part to the FUD (fear, uncertainty, and doubt) caused by these reviews.

On Sunday morning I came across an article  that describes how one PR firm allegedly hires interns “to trawl iTunes and other community forums posing as real users, and has them write positive reviews for their client’s applications.” Now, I knew that this sort of mischief happened, but I thought it was all amateurish behavior on the part of overzealous business owners and their fans. I did not realize it was an actual service one could select from a PR firm. How brazen!

On the other hand, maybe this article I read was actually secretly sponsored by a competing PR firm in order to discredit the PR firm being decried in the article. Who is to believe whom? Hmmm…..

Before you say that I am naïve about all this behavior, I’m not. The verification methodology survey I posted back in February was vandalized by VMM and OVM fans. And more than a year ago, someone copied a blog post of mine onto comp.lang.verilog for the sole purpose of posting in response a personal attack on my credibility. I’ve seen this stuff first hand.

A big part of the problem is anonymity and impunity. When someone uses a fictitious name and email address to post such a review as the one described above, we never know who that person is and he never suffers any consequences. After all, who is Vactioner287 after all? However, let’s say that one could only leave a comment by using his LinkedIn profile. I bet that would kill 99% of the issues right there.

(Actually, it would probably result in a proliferation of fictitious LinkedIn accounts, but then you could tell pretty well from those accounts that they are fakes since they’d be very bare. To some extent, like metastability, you can never totally get rid of the problem … you can only make it less likely.)

Most websites that accept reviews require registration. Although the hassle of registration deters some legitimate people from leaving legitimate comments, it also beneficially deters those with malicious intentions to a great degree. Almost all the online communities in EDA require some sort of registration, the Synopsys blogs being the only one that I can name that does not.

So, who ya gonna trust?

Personally, there are 3 types of people who I trust on the internet and they are as follows:

1. People I already know and trust - These are people who I know personally. Maybe they are current or former colleagues or customers or suppliers or partners or friends. I have reason to trust them because I know them.
2. People I’ve come to trust - These are people whom I have come to know through the internet who have demonstrated over a period of time that they are trustworthy. Maybe it’s a blogger who has proven to be right most of the time. Or whose advice rings true. Or who provides me with valuable information and insight. Hopefully, I am one of those people for you.
3. People I’ve been told to trust by others I trust - This is where social capital and influence come into play. If someone I trust links to someone else, then I gain trust in that person to whom he is linking. If he’s on his blogroll. If he’s a guest blogger. If he’s written a book that is referred to. Not that everyone that is referenced is automatically trustworthy, but it helps.

If you were to look at my Google Reader and see who I subscribe to, they pretty much fall into the 3 categories above. That gives me plenty to read.

Unfortunately, this doesn’t help too much with the situation I originally described, because Vacationer287 doesn’t fall any of these categories. What do you do then? Ask yourself the following:

1. Did he write anything else under this name or did he just join to post this one review. If the former, then he may be legit (you need to look at what they wrote). If the former, that’s suspicious.
2. Did he use a real name? Vandals often hide behind fictitious and non-descript names.
3. Does it pass the smell test? I can smell bad milk without a lab test and you can too. Does it all make sense or does some of the writeup just seem too good or bad to be true?

I don’t know if this post helps you or confuses you more. Probably, it confuses you because now you have to consider why and how you come to trust some people and not others on the internet. That’s good. From reconciling confusion comes understanding.

Trust me, you have my word on it.

harry the ASIC guy

Sean Murphy has the best one sentence description of DAC that I have ever read:

The emotional ambience at DAC is what you get when you pour the excitement of a high school science fair, the sense of the recurring wheel of life from the movie Groundhog Day, and the auld lang syne of a high school re-union, and hit frappe.

That perfectly describes my visit with Oasys Design Systems at DAC.

Auld Lang Syne

When I joined Synopsys in June of 1992, the company had already gone public, but still felt like a startup. Logic synthesis was going mainstream, challenging schematic entry for market dominance. ASICs (they were actually called gate arrays back then) were heading towards 50K gates capacity using 0.35 uM technology. And we were aiming to change the world by knocking off Joe Costello’s Cadence as the #1 EDA company.

As I walked through the Oasys booth at DAC, I recognized familiar faces. A former Synopsys sales manager, now a sales consultant for Oasys. A former Synopsys AE, now managing business development for Oasys. And not to be forgotten, Joe Costello, ever the Synopsys nemesis, now an Oasys board member. Even the company’s tag line “the chip synthesis company” is a takeoff on Synopsys’ original tag line “the synthesis company”. It seemed like 1992 all over again … only 17 years later.

Groundhog Day

In the movie Groundhog Day, Bill Murray portrays Phil, a smug, self-centered, yet popular TV reporter who is consigned by the spirits of Groundhog Day to relive Feb 2nd over and over. After many tries, Phil is finally able to live a “perfect day” that pleases the spirits and he is able to move on, as a better person, to Feb 3rd.

As I mentioned in a previous post, I’ve seen this movie before. In the synthesis market, there was Autologic on Groundhog Day #1. Then Ambit on Groundhod Day #2. Then Get2chip on Groundhod Day #3. Compass had a synthesis tool in there somewhere as well. (I’m sure Paul McLellan could tell me when that was.) None of these tools, some of which had significant initial performance advantages, were able to knock off Design Compiler as market leader. This Groundhog Day it’s Oasys’ turn. Will this be the day they finally “get it right”?

Science Fair

A good science fair project is part technology and part showmanship. Oasys had the showmanship with a pre-recorded 7-minute rock medley featuring “Bass ‘n’ Vocal Monster” Joe Costello, Sanjiv “Tropic Thunder” Kaul, and Paul “Van Halen” Besouw. Does anyone know if this has been posted on Youtube yet?

On the technology side, I had one main mission at the Oasys booth … to find out enough about the RealTime Designer product to make my own judgment whether it was “too good to be true”. In order to do this, I needed to get a better explanation of the algorithms working on “under-the-hood”, which I was able to get from founder Paul van Besouw.

For the demo, Paul ran on a Dell laptop with a 2.2 GHz Core Duo processor, although he claims that only 1 CPU was used. The demo design was a 1.6M instance design based on multiple instantiations of the open source Sparc T1 processor. The target technology was the open source 45nm Nangate library. Parts of the design flow ran in real time as we spoke about the tool, but unfortunately we did not run through the entire chip synthesis on his laptop in the 30 minutes I was there, so I cannot confirm the actual performance of the tool. Bummer.

Paul did describe, though, in some detail, the methods that enable their tool to achieve such fast turnaround time and high capacity. For some context, you need to go back in time to the origins and evolution of logic synthesis.

At 0.35 uM, gate delays were 80%+ of the path delay and the relatively small wire delays could be estimated accurately enough using statistical wire load models. At 0.25 uM, wire delays grew as a percentage of the path delay. The Synopsys Floorplan Manager tool allowed front-end designers to create custom wire load models from an initial floorplan. This helped maintain some accuracy for a while, but eventually was also too inaccurate. At 180 nM and 130 nM, Physical Compiler (now part of IC Compiler) came along to do actual cell placement and estimate wire lengths based on a global route. At 90 nM and 65 nM came DC-Topographic and DC-Graphical, further addressing the issues of wire delay accuracy and also layout congestion.

These approaches seem to work well, but certain drawbacks are starting to appear:

1. Much of the initial logic optimization takes place prior to placement, so the real delays (now heavily dependent on placement) are not available yet.
2. The capacity is limited because the logic optimization problem scales faster than order(n). Although Synopsys has come out with methods to address the turnaround time issue, such as automatic chip synthesis, these approaches amount to not much more than divide and conquer (i.e.budget and compile).
3. The placement developed by the front-end synthesis tool (e.g. DC-Topographic) is not passed on to the place and route tool. As a result, once you place the design again in the place and route tool, the timing has changed.

According to Paul van Besouw, Oasys decided to take an approach they call “place first”. That is, rather than spend a lot of cycles in logic optimization before even getting to placement, they do an initial placement of the design as soon as possible so they are working with real interconnect delays from the start. Because of this approach, RealTime Designer can get to meaningful optimizations almost immediately in the first stage of optimization.

A second key strategy according to van Besouw is the RTL partitioning which chops the design up into RTL blocks that are floorplaned and placed on the chip. The partitions are fluid, sometimes splitting apart, sometimes merging with other partitions during the optimization process as the design demands. The RTL can be revisited and changed for a new structure during the optimization as well. Since the RTL partitions are higher-level than gates, the number of design objects in much fewer, leading to faster runtime with lower memory foot print according to van Besouw. Exactly how Oasys does the RTL partitioning and optimizations is the “secret sauce”, so don’t expect to hear a lot of detail.

Besides this initial RTL optimization and placement, there are 2 more phases of synthesis in which the design is further optimized and refined to a legal placement. That final placement can be taken into any place and route tool and give you better results than the starting point netlist from another tool, says van Besouw.

In summary, Oasys claims that they achieve faster turnaround time and higher capacity by using a higher level of abstraction (RTL vs. gate). They claim that they can achieve a better starting point for and timing correlation with place and route because they use actual placement from the start and feed that placement on to the place and route tool. And the better placement also runs faster because it converges faster.

What Does Harry Think?

Given the description that I got from Oasys at DAC, I am now convinced that it is “plausible” that Oasys can do what they claim. Although gory detail is still missing, the technical approach described above sounds exactly right, almost obvious when you think about it. Add to that the advantage of starting from scratch with modern coding languages and methods and not being tied to a 20 year old code base, and you can achieve quite a bit of improvement.

However, until I see the actual tool running for myself in a neutral environment on a variety of designs and able to demonstrate faster timing closure through the place and route flow, I remain a skeptic. I’m not saying it is not real, just that I need to see it.

There are several pieces of the solution that were not addressed adequately, in my opinion:

1. Clock tree synthesis - How can you claim to have a netlist and placement optimized to meet timing until you have a clock tree with its unique slew and skew. CTS is not address in this solution. (To be fair, it’s not addressed directly in Design Compiler either).
2. A robust interface to the backend - Oasys has no backend tools in-house, which means that the work they have done integrating with 3rd party place and route has been at customer sites, either by them or by the customer. How robust could those flows be unless they have the tools in-house (and join the respective partner programs).
3. Bells and whistles - RealTime designer can support multi-voltage, but not multi-mode optimization. Support for low power design is not complete. What about UPF? CPF? All of these are important in a real flow and it is not clear what support Oasys has.
4. Tapeouts - This is probably the key question. For as long as EDA has existed, tapeouts have been the gold standards by which to evaluate a tool and its adoption. When I asked Paul if there are any tapeouts to date, he said “probably”. That seems odd to me. He should know.

However, if Oasys can address these issues, this might actually be the game changer that gets us out of the Groundhog Day rut and onto a new day.

harry the ASIC guy

(Photo courtesy J.L. Gray) 

Last year, at the Design Automation Conference, there were only a couple dozen individuals who would have merited the title of EDA blogger. Of those, perhaps a dozen or so wrote regularly and had any appreciable audience. In order to nurture this fledgling group, JL Gray (with the help of John Ford, Sean Murphy, and yours truly) scrounged a free room after-hours in the back corner of the Anaheim Convention Center in which to hold the first ever EDA Bloggers Birds-of-a-Feather session. At this event, attended by both bloggers and traditional journalists, as John Ford put it, us bloggers got our collective butts sniffed by the top dog journalists.

My, how things have changed in just one year.

This year at DAC, us EDA bloggers (numbering 233 according to Sean Murphy) and other new media practitioners took center stage:

• Bloggers were literally on stage at the Denali party as part of an EDA’s Next Top Blogger competition.
• Bloggers were literally center stage at the exhibits, in the centrally located Synopsys booth, engaging in lively conversation regarding new media.
• Atrenta held a Blogfest.
• There was a Pavillion Panel dedicated to tweeting and blogging.
• And most conspicuously, there was the 14-foot Twitter Tower streaming DAC related tweets.

Meanwhile, the traditional journalists who were still covering DAC seemed to fall into 2 camps. There were those who embraced the bloggers as part of the media and those that didn’t. Those that did, like Brian Fuller, could be found in many of the sessions and venues I mentioned above. Those that did not, could be found somewhere down the hall between North and South halls of Moscone in their own back corner room. I know this because I was given access to the press room this year and I did indeed find that room to be very valuable … I was able to print out my boarding pass on their printer.

Here’s my recap of the new media events:

I had mixed feelings regarding the Denali Top Blogger competition as I know others did as well. JL, Karen, and I all felt it was kind of silly, parading like beauty queens to be judged. Especially since blogging is such a collaborative, rather than competitive, medium. So often we reference and riff off of each other’s blog posts. Still, I think it was good recognition and publicity for blogging in EDA and one could not argue with the legitimacy of the blogger representatives, all first-hand experts in the areas that they cover. Oh, by the way, congratulations to Karen Bartleson for winning the award.

Conversation Central, hosted by Synopsys, was my highlight of DAC.  It was a little hard to find (they should have had a sign), located in a little frosted glass room on the left front corner of the Synopsys booth. But if you could find your way there, it was well worth the search. I’m a little biased since I hosted conversations there Monday - Wednesday on “Job Search: How Social Media Can Help Job Seekers & Employers”. The sessions were a combination of specific advice and lively discussions and debates. I was fortunate to have a recruiter show up one day and a hiring manager another day to add their unique perspectives. I think that that was the real power of this very intimate kitchen table style format. Everybody felt like they were allowed to and even encouraged to participate and add their views into the discussions. This is very different from a very formal style presentation and even panel discussions.

Unfortunately, I was not able to clone myself in order to attend all the sessions there, many of which I heard about afterwards from others or in online writeups. I did attend the session by Ron Ploof entitled “Objectivity is Overrated: Corporate Bloggers Aren’t Journalists, & Why They Shouldn’t Even Try”. Interestingly enough, no journalists showed up to the session. Still, it was a lively discussion, the key point being that bloggers don’t just talk the talk, they walk the walk, and therefore bring to the table a deeper understanding and experience with EDA and design than a journalist, even one that was previously a designer.

I also attended Rick Jamison’s session on “Competitors in Cyberspace: Why Be Friends?” which attracted several Cadence folks (Joe Hupcey, Adam Sherer, Bob Dwyer) and some Mentor folks. Although competitors for their respective companies, there was a sense of fraternity and a lot of the discussion concerned what is “fair play” with regards to blog posting and commenting. The consensus was that advocacy was acceptable and even expected from the partisans, as long as it could be backed up by fact and kept within the bounds of decorum (i.e. no personal attacks). EDA corporate bloggers have been very fair in this regards in contrast to some rather vitriolic “discussions” in other industries.

The Atrenta Blogfest sounded very interesting and I was very disappointed that I could not attend because it conflicted with my Conversation Central discussion. Mike Demler has a brief summary on his blog as does Daniel Nenni on his blog.

Late Wednesday, Michael Sanie hosted a DAC Pavillion Panel entitled “Tweet, Blog or News: How Do I Stay Current?” Panelists Ron Wilson (Practical Chip Design in EDN), John Busco (John’s Semi-Blog) and Sean Murphy (his blog) shared insights into the ways they use social media to stay current with events in the industry, avoid information overload, and separate fact from fiction. Ron Wilson commented that social networks are taking the place of the socialization that engineers used to get by attending conferences and the shared experience reading the same traditional media news. John Busco, the recognized first EDA blogger, shared how he keeps his private life and his job at NVidia separate from his blogging life. And Sean Murphy gave perspective on how blogging has grown within EDA and will continue to grow to his projection of 500 EDA bloggers in 2011.

Last, but not least, there was the Twitter Tower, located next to the Synopsys booth. Previous conferences, such as DVCon attempted to use hashtags (#DVCon) to aggregate conference related tweets. The success was limited, attracting perhaps a few dozen tweets at most. This time, Karen Bartleson had a better idea. Appeal to people’s vanity. The Twitter Tower displayed a realtime snapshot of all tweets containing “#46DAC“, the hashtag designated for the 46th DAC. If one stood in front of the tower and tweeted with this hastag, the tweet would show up within seconds on the tower. How cool is that? Sure it was a little gimmicky, but it made everyone who passed by aware of this new standard. As I write this, there have been over 1500 tweets using the #46DAC hashtag.

If you want to read more, Sean Murphy has done the not-so-glamorous but oh-so-valuable legwork of compiling a pretty comprehensive roundup of the DAC coverage by bloggers and traditional press. (Thanks Sean!)

harry the ASIC guy

I’m writing to you today from a Coffee Bean & Tea Leaf in beautiful Southern California. There’s something about the atmosphere at a coffee shop that helps me get my thoughts together. Maybe it’s the white noise of the cappuccino machines or the conversations or music in the background.

I’m not the only one of course. Daniel Nenni and his two great danes can often be found at the downtown Danville Starbucks. And like the show Cheers, there are regulars at my local coffee shop that I see most days I am here. Sales people and college students come here a lot. And there has been a noticeable increase in another group. People out of work or “in transition”. In fact, as I glance over to the next table, I see a woman working on her resume. No lie.

Despite the uncertainty, I’ve actually benefited from the opportunity to take a one month break between projects, something I never got as a full-time employee. I’ve been able to catch up with old friends and colleagues on the phone, or over coffee, lunch, or some beers. I’ve also been able to start up some new business opportunities that you’ll be hearing more about in the near future. It never hurts to have multiple irons in the fire, especially in today’s economy.

Which brings me to the topic of jobs. I don’t care what any politician or semiconductor analyst or economist says or what the Dow or NASDAQ is at today. The high tech jobs market sucks. When I ask my very experienced friends and colleagues “what’s happening” they tell me they “can’t find no work, can’t find no job, my friend”. (Marvin Gaye fans will get the reference). Here are some examples:

• Al Magnani, a friend in the Bay Area with 23 years experience, educated at MIT, USC, and Carnegie-Mellon, an expert in computer architecture, networking, and graphics processing, who’s led dozens of ASIC design developments, who’s been a Director managing a total team of over 50 people, has gone through almost all of his 229 LinkedIn contacts and has not even been able to get an interview in almost 2 months.
• Jon Atwood, former VP of Sales at Synopsys and a man who has so much EDA experience that he remembers Joe Costello before he played guitar, has been looking for almost 6 months and has started a blog called Job Search 2.0 chronicling his job search adventure. He’s even been on ABC news talking about his employment woes.
• I’ve received emails from several other very experienced designers, both employees and independent consultants, who tell similar stories of months looking for work.
• On a personal level, as I have been looking for that “next project”, I have encountered much of the same, and count myself lucky that I actually have a next project to work on.

Having talked to so many of these people and recruiters, here is how I assess the high-tech job situation today:

• There are a lot more job seekers than jobs out there. OK, that’s obvious. But to give you an idea, of the magnitude, my recruiter friend says she receives hundreds of resumes for every job posted and there are usually many, sometimes dozens of, qualified candidates to choose from.
• Many of the job postings are soft. That is, the employer does not need to hire someone right away but just has the job posted in case the perfect candidate comes along.
• Employers are looking for the perfect candidate to come along. If they have 10 requirements for the position, and you meet 9 of them, you are probably on the B-list. And not only are they looking for the right experience, they want you to have been doing pretty much the same job very recently, not 2 years ago.
• Submitting your resume to a corporate website is a waste of time. Even if you are perfectly qualified, recruiters get too many job postings and your resume may not even get looked at because they run out of time and already have many candidates.
• Experience counts … against you. Many employers are looking for younger people who don’t have high salary expectations and will work long hours and travel. In fact, I spoke to a recruiter that was retained by a recent chip synthesis startup that told me that he was only looking for candidates with <5 years experience to be an AE at that company. They are not the only ones.
• Employers hold all the cards. I heard today about someone who accepted a job at 10% less than she was currently making. Don’t expect to make more or even as much as you made before. Don’t expect stock options or signing bonuses. And don’t expect more than 24 hours to make a decision on an offer because there is someone on-deck.

So, with the news that bad, it would be easy to get discouraged. I have been discouraged, for myself and for my friends. Still, here are a few tips that I think will help:

1. Update your online identity. Every recruiter and hiring manager will do 2 things before they ever pick up the phone and call you. They will Google your name and they will search for you on LinkedIn. Space prohibits me from going into the details of how to do this, but believe me that this is critical. If you want to see an example, you can see my LinkedIn profile.
2. Find someone in the company who can introduce you or your resume to the hiring manager with a recommendation. This has always been the best way to find a job, but today it is the only way. As I said, the odds of you making it through the corporate website and HR are very low. LinkedIn can help tremendously since you can identify easily who you know at a target company and also whether your contacts know somebody there to whom they can introduce you.
3. Let your contact refer you before you submit anything to the corporate website. Even in this economy, many companies still give bonuses to employees who refer candidates. If you let your contact get the referral bonus, he will be more likely to help you find the right people in the company to talk to and even sell you to them.
4. Sign up for job boards. I know that everyone else is using these, but there are still real jobs posted there and you can get an idea which companies are hiring and then use your networking skills to get in the door. Simplyhired and even craigslist are good.
5. Be willing to take a step back to go forward. You will probably need to a take a cut in pay or take on a position with less responsibility or prestige than you currently have. Accept it. I have a friend who refused to look at jobs that paid less than he previously made. He ended up out of work for 6 months and then ended up taking a lower paying job anyway. It’s more important that you get a job you can do well and that the company has a good outlook going forward.
6. Help others find a job. You can file this under good karma, or pay it forward, or just plain being a mentsch. If you come across a position for which someone you know would be a good fit, let them know, help them out. It will make you feel a little better and you’ll have made a loyal friend who may be in a position to help you out one day soon.
7. Get into social networking. I’ll be talking about this more at DAC, but for now, look for opportunities to get on Twitter. Start reading, commenting on, or even writing a blog. Join relevant LinkedIn groups. Join online communities like those at Synopsys, Mentor, and Cadence or independent ones like OVMWorld or Xuropa.
8. Keep up your skills. There are so many free webinars and opportunities to keep up-to-date that you have no excuse. Check out the Mentor Displaced Worker program.
9. Consider doing some free work. I know that does not sound great, but you can possibly learn something new in the process and at least avoid having a gap in your resume (remember how picky employers are).
10. Decide if you are willing to relocate or travel. If you are only looking for positions within your commuting distance then that limits your opportunities.

For those of you who will be attending DAC this coming week, I will be in the Synopsys Conversation Central booth Monday, Tuesday, and Wednesday at 1:30 hosting a conversation on Using Social Media for Job Seekers and Employers.

Please stop and we can talk over a cup of coffee.

harry the ASIC guy

That’s the question that everyone was asking last week when Oasys Design Systems came out of stealth mode with a “chip synthesis” tool they claim leaves Synopsys’ Design Compiler and other synthesis tools in the dust. According to Sanjiv Kaul, Chairman of Oasys and former VP of Synopsys’ Implementation Business Unit, RealTime Designer can synthesize full chips up to 100 million gates in a single run, and do so 20x faster with smaller memory requirements and achieving better quality of results. Oh, and it also produces a legalized cell placement that can be taken forward into detailed routing.

Well, I had 3 different reactions to these claims:

1. “Too good to be true!”

This was also the most common reaction I heard from fellow designers when I told them of the Oasys claims. It was my own reaction a month or so ago when I first spoke to Oasys about their technology. (To tell the truth, I was wondering what they were smoking.) Paul McLellan, as of last week a blogger for Oasys, indicated that disbelief was the most common reaction heard from people Oasys talks to about this product. Steve Meier, former VP of R&D for IC Compiler at Synopsys, said the same thing on Twitter and added some specific questions for Oasys to answer. Even one of the Oasoids (is it to early to coin that phrase) acknowledged to me privately that he was incredulous when he was first approached months ago to join the team. I guess he was convinced enough to join.

2. “I’ve seen this movie before, and I know how it ends.”

That was my second reaction. After all, there were Synopsys killers before. Ambit (out of which, by the way, came most of the developers of the Oasys tool) was the first big threat. They had a better QOR (quality of results) by many accounts, but Synopsys responded quickly to stave them off. Then came Get2Chip. Similar story. Cadence’s RTL Compiler, which combines technology from both Ambit and Get2Chip, is well regarded by many but still it has a very small market share. Bottom line, nobody ever got fired for choosing Design Compiler, so it’s hard to imagine a mass migration. Still, if the Oasys claims are true, they’d have a much more compelling advantage than Ambit or Get2Chip ever had.

3. “Synthesis? Who cares about synthesis?”

That’s my third reaction. Verification is the #1 problem for ASIC design teams. DFM is a critical issue. ESL and C-synthesis are starting to take off. RTL synthesis addresses none of these big problems or opportunities. It’s a solved problem. Indeed, many design flows just do a “quick and dirty” synthesis in order to get a netlist in to place and route where real timing can be seen and a good placement performed. I hear very few people complaining about synthesis, so I wonder who is going to spend money in a tight economy on something that just “ain’t broken”. True, synthesis may be a bottleneck for 100M gate ASICs, but how many companies are doing those and can those companies alone support Oasys. If you talk to Oasys, however, they feel that the availability of such fast synthesis will change the way people design, creating a “new platform”. I’m not sure I see that, but perhaps they are smarter than me.

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OK, so that’s my first 3 thoughts regarding Oasys design. I’ll be getting a better look at them at DAC and will share what I learn in some upcoming blog posts. Please feel free to share your thoughts here as well. Between us, we can hopefully decide if this Oasys is real or a mirage.

harry the ASIC guy

By Narendra (Nari) Shenoy, Technical Program Co-Chair, 46th DAC

Each year, around this time, the electronic design industry and academia meticulously prepare to showcase the latest research and technologies at the Design Automation Conference. For the casual attendee, after a few years the difference between the conferences of years past begins to dim. If you are one of them, allow me to dispel this notion and invite you to look at what is different this year.

For starters, we will be in the beautiful city of San Francisco from July 26-31. The DAC 2009 program, as in previous years, has been thoughtfully composed from using two approaches. The bottom up approach selects technical papers from a pool of submissions using a rigorous review process. This ensures that only the best technical submissions are accepted. For 2009, we see an increasing focus on research towards system level design, low power design and analysis, and physical design and manufacturability. This year, a special emphasis for the design community has been added to the program, with a User Track that runs throughout the conference. The new track, which focuses on the use of EDA tools, attracted 117 submissions reviewed by a committee made up of experienced tool users from the industry. The User Track features front end and back end sessions and a poster session that allows a perfect opportunity to interact with presenters and other DAC attendees. In addition to the traditional EDA professionals, we invite all practitioners in the design community – design tool users, hardware and software designers, application engineers, consultants, and flow/methodology developers, to come join us.

This first approach is complemented by a careful top-down selection of themes and topics in the form of panels, special sessions, keynote sessions, and management day events. The popular CEO panel returns to DAC this year as a keynote panel. The captains of the EDA industry, Aart deGeus (Synopsys), Lip-Bu Tan (Cadence) and Walden Rhines (Mentor) will explore what the future holds for EDA. The keynote on Tuesday by Fu-Chieh Hsu (TSMC), will discuss alignment of business and technology models to overcome design complexity. William Dally (Nvidia and Stanford) will present the challenges and opportunities that throughput computing provides to the EDA world in his keynote on Wednesday. Eight panels on relevant areas are spread across the conference. One panel explores whether the emphasis on Design for Manufacturing is a differentiator or a distraction. Other panels focus on a variety of themes such as confronting hardware-dependent software design, analog and mixed signal verification challenges, and various system prototyping approaches. The financial viability of Moore’s law is explored in a panel, while another panel explores the role of statistical analysis in several fields, including EDA. Lastly, we have a panel exploring the implications of recent changes in the EDA industry from an engineer’s perspective.

Special technical sessions will deal with a wide variety of themes such as preparing for design at 22nm, designing circuits in the face of uncertainty, verification of large systems on chip, bug-tracking in complex designs, novel computation models and multi-core computing. Leading researchers and industry experts will present their views on each of these topics.

Management day includes topics that tackle challenges and decision making in a complex technology and business environment. The current “green” trend is reflected in a slate of events during the afternoon of Thursday July 30th. We start with a special plenary that explores green technology and its impact on system design, public policy and our industry. A special panel investigates the system level power design challenge and finally a special session considers technologies for data centers.

Rather than considering it a hindrance to attendance, the prolonged economic malaise this year should provide a fundamental reason to participate at DAC. As a participant in the technical program, DAC offers an opportunity to share your research and win peer acclaim. As an exhibitor, it is an ideal environment to demonstrate your technology and advance your business agenda. As an attendee, you cannot afford to miss the event where “electronic design meets”. DAC provides an unparalleled chance to network and learn about advances in electronic design for everyone. Won’t you join us at the Moscone Center at the end of the month?

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This year’s DAC will be held July 26-31 at the Moscone Center in San Francisco. Register today at www.dac.com. Note also that there are 600 free DAC passes being offered courtesy of the DAC Fan Club (Atrenta, Denali, Springsoft) for those who have no other means to attend.

(WARNING: What you are about to hear is very disturbing. You may want to remove any children, pets, or small farm animals before listening to the audio in this blog post. You’ve been warned.)

Several years ago, I was driving home from a family vacation when I accidentally speed dialed my boss on the cell phone. His voice mail picked up just as I was singing in the car to my daughter. I had no idea what had occurred until a month later at a staff meeting when he got up in from of my team and my colleagues and played this audio track.

Now you know why I am not trying to become the next EDA Idol at this year’s Design Automation Conference!

Fortunately, there is another tongue-in-cheek contest that I am honored to be part of, EDA’s Next Top Blogger.

In case you can’t make DAC this year, I’d like to introduce you to the fellow nominees because they are all great writers and experts in their domains. I encourage you to read these blogs and subscribe to the ones that you find valuable. And look beyond this list because there are many more out there.

Colin Warwick is a Product Marketing Manager at Agilent EEsof EDA group. Colin’s Signal Integrity blog is about signal integrity tips, tricks, and tutorial for multigigabit/s chip-to-chip data links. It includes videos (technical and humorous), tutorial articles, interactive calculators and polls, reviews, and product and event information.

John Busco is a Design Implementation Manager at NVidia. Blogging since 2005, John’s Semi-Blog shares high quality news and opinion about semiconductors and EDA. John is hands-on working in the trenches on the bleeding edge designs, so you can trust what he tells you.

Paul McLellan  has been an executive in EDA and Semiconductors with companies like VLSI Technologies, Compass, Ambit, Cadence,and on and on. His EDA Graffiti blog covers EDA and semiconductor, looking back to some history, analyzing the industry and looking where things are likely to end up. I always walk away from Paul’s blog posts with something to think about.

Daniel Nenni is also an EDA industry veteran with similarly impressive credentials. Although his Silicon Valley Blog is fairly new, Daniel writes like a verteran blogger, sharing his 25+ years of experience in semiconductor design and manufacture in an entertaining manner. He manages to share some of his personal life observations as well.

Karen Bartleson is Director of Community Marketing at Synopsys. Since November 2007, she has presented news, insights, and opinions on the topic of EDA standards in her ever popular The Standards Game blog. Karen is also spearheading Synopsys’ Conversation Central at DAC where you can exchange ideas with many of these same top bloggers (and many more) about how social media is changing the media landscape.

Frank Schirrmeister is Director of Product Marketing and System-Level Solutions at Synopsys. His A View From The Top blog is dedicated to System-Level Design and Embedded Software and deals with the technology and business aspects to get us to ESL and the next abstraction level eventually!

JL Gray is a hands-on verification consultant at Verilab. In his Cool Verification blog, which set the standard for independent blogging in EDA, JL shares this thoughts on hardware verification, the EDA industry, and related topics. JL spearheaded the EDA Blogger Birds-of-a-Feather session at DAC last year and sits on the ever popular Accellera Verification IP Technical Subcommittee.

I have 2 favors to ask. First, please check out some these wonderful bloggers (and some of the others you can find on David Lin’s EDA Blog Roll) who devote their evenings and weekends writing for free (well, about half of us) to bring you valuable information you can’t get anywhere else. Then, show your support by voting for your favorite blog and telling a friend or a co-worker about all this great content out there. Please vote for whoever you want, but remember, if I lose, I might have to sing next year. And you don’t want that!

(Note: The Denali site requires you to enter a Captcha phrase and also your valid email address in order to ensure that people only vote once. The email address WILL NOT be used for any other purpose, so please do not be dissuaded from voting because of this).

harry the ASIC guy