Posts Tagged ‘Synopsys’

DAC Theme #1 - “The Rise of the EDA Bloggers”

Sunday, August 2nd, 2009

Harry Gries at Conversation Central

(Photo courtesy J.L. Gray

Last year, at the Design Automation Conference, there were only a couple dozen individuals who would have merited the title of EDA blogger. Of those, perhaps a dozen or so wrote regularly and had any appreciable audience. In order to nurture this fledgling group, JL Gray (with the help of John Ford, Sean Murphy, and yours truly) scrounged a free room after-hours in the back corner of the Anaheim Convention Center in which to hold the first ever EDA Bloggers Birds-of-a-Feather session. At this event, attended by both bloggers and traditional journalists, as John Ford put it, us bloggers got our collective butts sniffed by the top dog journalists.

My, how things have changed in just one year.

This year at DAC, us EDA bloggers (numbering 233 according to Sean Murphy) and other new media practitioners took center stage:

  • Bloggers were literally on stage at the Denali party as part of an EDA’s Next Top Blogger competition.
  • Bloggers were literally center stage at the exhibits, in the centrally located Synopsys booth, engaging in lively conversation regarding new media.
  • Atrenta held a Blogfest.
  • There was a Pavillion Panel dedicated to tweeting and blogging.
  • And most conspicuously, there was the 14-foot Twitter Tower streaming DAC related tweets.

Meanwhile, the traditional journalists who were still covering DAC seemed to fall into 2 camps. There were those who embraced the bloggers as part of the media and those that didn’t. Those that did, like Brian Fuller, could be found in many of the sessions and venues I mentioned above. Those that did not, could be found somewhere down the hall between North and South halls of Moscone in their own back corner room. I know this because I was given access to the press room this year and I did indeed find that room to be very valuable … I was able to print out my boarding pass on their printer.

Here’s my recap of the new media events:

I had mixed feelings regarding the Denali Top Blogger competition as I know others did as well. JL, Karen, and I all felt it was kind of silly, parading like beauty queens to be judged. Especially since blogging is such a collaborative, rather than competitive, medium. So often we reference and riff off of each other’s blog posts. Still, I think it was good recognition and publicity for blogging in EDA and one could not argue with the legitimacy of the blogger representatives, all first-hand experts in the areas that they cover. Oh, by the way, congratulations to Karen Bartleson for winning the award.

Conversation Central, hosted by Synopsys, was my highlight of DAC.  It was a little hard to find (they should have had a sign), located in a little frosted glass room on the left front corner of the Synopsys booth. But if you could find your way there, it was well worth the search. I’m a little biased since I hosted conversations there Monday - Wednesday on “Job Search: How Social Media Can Help Job Seekers & Employers”. The sessions were a combination of specific advice and lively discussions and debates. I was fortunate to have a recruiter show up one day and a hiring manager another day to add their unique perspectives. I think that that was the real power of this very intimate kitchen table style format. Everybody felt like they were allowed to and even encouraged to participate and add their views into the discussions. This is very different from a very formal style presentation and even panel discussions.

Unfortunately, I was not able to clone myself in order to attend all the sessions there, many of which I heard about afterwards from others or in online writeups. I did attend the session by Ron Ploof entitled “Objectivity is Overrated: Corporate Bloggers Aren’t Journalists, & Why They Shouldn’t Even Try”. Interestingly enough, no journalists showed up to the session. Still, it was a lively discussion, the key point being that bloggers don’t just talk the talk, they walk the walk, and therefore bring to the table a deeper understanding and experience with EDA and design than a journalist, even one that was previously a designer.

I also attended Rick Jamison’s session on “Competitors in Cyberspace: Why Be Friends?” which attracted several Cadence folks (Joe Hupcey, Adam Sherer, Bob Dwyer) and some Mentor folks. Although competitors for their respective companies, there was a sense of fraternity and a lot of the discussion concerned what is “fair play” with regards to blog posting and commenting. The consensus was that advocacy was acceptable and even expected from the partisans, as long as it could be backed up by fact and kept within the bounds of decorum (i.e. no personal attacks). EDA corporate bloggers have been very fair in this regards in contrast to some rather vitriolic “discussions” in other industries.

The Atrenta Blogfest sounded very interesting and I was very disappointed that I could not attend because it conflicted with my Conversation Central discussion. Mike Demler has a brief summary on his blog as does Daniel Nenni on his blog.

Late Wednesday, Michael Sanie hosted a DAC Pavillion Panel entitled “Tweet, Blog or News: How Do I Stay Current?” Panelists Ron Wilson (Practical Chip Design in EDN), John Busco (John’s Semi-Blog) and Sean Murphy (his blog) shared insights into the ways they use social media to stay current with events in the industry, avoid information overload, and separate fact from fiction. Ron Wilson commented that social networks are taking the place of the socialization that engineers used to get by attending conferences and the shared experience reading the same traditional media news. John Busco, the recognized first EDA blogger, shared how he keeps his private life and his job at NVidia separate from his blogging life. And Sean Murphy gave perspective on how blogging has grown within EDA and will continue to grow to his projection of 500 EDA bloggers in 2011.

Last, but not least, there was the Twitter Tower, located next to the Synopsys booth. Previous conferences, such as DVCon attempted to use hashtags (#DVCon) to aggregate conference related tweets. The success was limited, attracting perhaps a few dozen tweets at most. This time, Karen Bartleson had a better idea. Appeal to people’s vanity. The Twitter Tower displayed a realtime snapshot of all tweets containing “#46DAC“, the hashtag designated for the 46th DAC. If one stood in front of the tower and tweeted with this hastag, the tweet would show up within seconds on the tower. How cool is that? Sure it was a little gimmicky, but it made everyone who passed by aware of this new standard. As I write this, there have been over 1500 tweets using the #46DAC hashtag.

If you want to read more, Sean Murphy has done the not-so-glamorous but oh-so-valuable legwork of compiling a pretty comprehensive roundup of the DAC coverage by bloggers and traditional press. (Thanks Sean!)

harry the ASIC guy

Coffee, Jobs, and DAC

Sunday, July 26th, 2009

Coffeeshop

I’m writing to you today from a Coffee Bean & Tea Leaf in beautiful Southern California. There’s something about the atmosphere at a coffee shop that helps me get my thoughts together. Maybe it’s the white noise of the cappuccino machines or the conversations or music in the background.

I’m not the only one of course. Daniel Nenni and his two great danes can often be found at the downtown Danville Starbucks. And like the show Cheers, there are regulars at my local coffee shop that I see most days I am here. Sales people and college students come here a lot. And there has been a noticeable increase in another group. People out of work or “in transition”. In fact, as I glance over to the next table, I see a woman working on her resume. No lie.

Despite the uncertainty, I’ve actually benefited from the opportunity to take a one month break between projects, something I never got as a full-time employee. I’ve been able to catch up with old friends and colleagues on the phone, or over coffee, lunch, or some beers. I’ve also been able to start up some new business opportunities that you’ll be hearing more about in the near future. It never hurts to have multiple irons in the fire, especially in today’s economy.

Which brings me to the topic of jobs. I don’t care what any politician or semiconductor analyst or economist says or what the Dow or NASDAQ is at today. The high tech jobs market sucks. When I ask my very experienced friends and colleagues “what’s happening” they tell me they “can’t find no work, can’t find no job, my friend”. (Marvin Gaye fans will get the reference). Here are some examples:

  • Al Magnani, a friend in the Bay Area with 23 years experience, educated at MIT, USC, and Carnegie-Mellon, an expert in computer architecture, networking, and graphics processing, who’s led dozens of ASIC design developments, who’s been a Director managing a total team of over 50 people, has gone through almost all of his 229 LinkedIn contacts and has not even been able to get an interview in almost 2 months.
  • Jon Atwood, former VP of Sales at Synopsys and a man who has so much EDA experience that he remembers Joe Costello before he played guitar, has been looking for almost 6 months and has started a blog called Job Search 2.0 chronicling his job search adventure. He’s even been on ABC news talking about his employment woes.
  • I’ve received emails from several other very experienced designers, both employees and independent consultants, who tell similar stories of months looking for work.
  • On a personal level, as I have been looking for that “next project”, I have encountered much of the same, and count myself lucky that I actually have a next project to work on.

Having talked to so many of these people and recruiters, here is how I assess the high-tech job situation today:

  • There are a lot more job seekers than jobs out there. OK, that’s obvious. But to give you an idea, of the magnitude, my recruiter friend says she receives hundreds of resumes for every job posted and there are usually many, sometimes dozens of, qualified candidates to choose from.
  • Many of the job postings are soft. That is, the employer does not need to hire someone right away but just has the job posted in case the perfect candidate comes along.
  • Employers are looking for the perfect candidate to come along. If they have 10 requirements for the position, and you meet 9 of them, you are probably on the B-list. And not only are they looking for the right experience, they want you to have been doing pretty much the same job very recently, not 2 years ago.
  • Submitting your resume to a corporate website is a waste of time. Even if you are perfectly qualified, recruiters get too many job postings and your resume may not even get looked at because they run out of time and already have many candidates.
  • Experience counts … against you. Many employers are looking for younger people who don’t have high salary expectations and will work long hours and travel. In fact, I spoke to a recruiter that was retained by a recent chip synthesis startup that told me that he was only looking for candidates with <5 years experience to be an AE at that company. They are not the only ones.
  • Employers hold all the cards. I heard today about someone who accepted a job at 10% less than she was currently making. Don’t expect to make more or even as much as you made before. Don’t expect stock options or signing bonuses. And don’t expect more than 24 hours to make a decision on an offer because there is someone on-deck.

So, with the news that bad, it would be easy to get discouraged. I have been discouraged, for myself and for my friends. Still, here are a few tips that I think will help:

  1. Update your online identity. Every recruiter and hiring manager will do 2 things before they ever pick up the phone and call you. They will Google your name and they will search for you on LinkedIn. Space prohibits me from going into the details of how to do this, but believe me that this is critical. If you want to see an example, you can see my LinkedIn profile.
  2. Find someone in the company who can introduce you or your resume to the hiring manager with a recommendation. This has always been the best way to find a job, but today it is the only way. As I said, the odds of you making it through the corporate website and HR are very low. LinkedIn can help tremendously since you can identify easily who you know at a target company and also whether your contacts know somebody there to whom they can introduce you.
  3. Let your contact refer you before you submit anything to the corporate website. Even in this economy, many companies still give bonuses to employees who refer candidates. If you let your contact get the referral bonus, he will be more likely to help you find the right people in the company to talk to and even sell you to them.
  4. Sign up for job boards. I know that everyone else is using these, but there are still real jobs posted there and you can get an idea which companies are hiring and then use your networking skills to get in the door. Simplyhired and even craigslist are good.
  5. Be willing to take a step back to go forward. You will probably need to a take a cut in pay or take on a position with less responsibility or prestige than you currently have. Accept it. I have a friend who refused to look at jobs that paid less than he previously made. He ended up out of work for 6 months and then ended up taking a lower paying job anyway. It’s more important that you get a job you can do well and that the company has a good outlook going forward.
  6. Help others find a job. You can file this under good karma, or pay it forward, or just plain being a mentsch. If you come across a position for which someone you know would be a good fit, let them know, help them out. It will make you feel a little better and you’ll have made a loyal friend who may be in a position to help you out one day soon.
  7. Get into social networking. I’ll be talking about this more at DAC, but for now, look for opportunities to get on Twitter. Start reading, commenting on, or even writing a blog. Join relevant LinkedIn groups. Join online communities like those at Synopsys, Mentor, and Cadence or independent ones like OVMWorld or Xuropa.
  8. Keep up your skills. There are so many free webinars and opportunities to keep up-to-date that you have no excuse. Check out the Mentor Displaced Worker program.
  9. Consider doing some free work. I know that does not sound great, but you can possibly learn something new in the process and at least avoid having a gap in your resume (remember how picky employers are).
  10. Decide if you are willing to relocate or travel. If you are only looking for positions within your commuting distance then that limits your opportunities.

For those of you who will be attending DAC this coming week, I will be in the Synopsys Conversation Central booth Monday, Tuesday, and Wednesday at 1:30 hosting a conversation on Using Social Media for Job Seekers and Employers.

Please stop and we can talk over a cup of coffee.

harry the ASIC guy

Oasys or Mirage?

Monday, July 20th, 2009

Oasis BMP

That’s the question that everyone was asking last week when Oasys Design Systems came out of stealth mode with a “chip synthesis” tool they claim leaves Synopsys’ Design Compiler and other synthesis tools in the dust. According to Sanjiv Kaul, Chairman of Oasys and former VP of Synopsys’ Implementation Business Unit, RealTime Designer can synthesize full chips up to 100 million gates in a single run, and do so 20x faster with smaller memory requirements and achieving better quality of results. Oh, and it also produces a legalized cell placement that can be taken forward into detailed routing.

Well, I had 3 different reactions to these claims:

1. “Too good to be true!”

This was also the most common reaction I heard from fellow designers when I told them of the Oasys claims. It was my own reaction a month or so ago when I first spoke to Oasys about their technology. (To tell the truth, I was wondering what they were smoking.) Paul McLellan, as of last week a blogger for Oasys, indicated that disbelief was the most common reaction heard from people Oasys talks to about this product. Steve Meier, former VP of R&D for IC Compiler at Synopsys, said the same thing on Twitter and added some specific questions for Oasys to answer. Even one of the Oasoids (is it to early to coin that phrase) acknowledged to me privately that he was incredulous when he was first approached months ago to join the team. I guess he was convinced enough to join.

2. “I’ve seen this movie before, and I know how it ends.”

That was my second reaction. After all, there were Synopsys killers before. Ambit (out of which, by the way, came most of the developers of the Oasys tool) was the first big threat. They had a better QOR (quality of results) by many accounts, but Synopsys responded quickly to stave them off. Then came Get2Chip. Similar story. Cadence’s RTL Compiler, which combines technology from both Ambit and Get2Chip, is well regarded by many but still it has a very small market share. Bottom line, nobody ever got fired for choosing Design Compiler, so it’s hard to imagine a mass migration. Still, if the Oasys claims are true, they’d have a much more compelling advantage than Ambit or Get2Chip ever had.

3. “Synthesis? Who cares about synthesis?”

That’s my third reaction. Verification is the #1 problem for ASIC design teams. DFM is a critical issue. ESL and C-synthesis are starting to take off. RTL synthesis addresses none of these big problems or opportunities. It’s a solved problem. Indeed, many design flows just do a “quick and dirty” synthesis in order to get a netlist in to place and route where real timing can be seen and a good placement performed. I hear very few people complaining about synthesis, so I wonder who is going to spend money in a tight economy on something that just “ain’t broken”. True, synthesis may be a bottleneck for 100M gate ASICs, but how many companies are doing those and can those companies alone support Oasys. If you talk to Oasys, however, they feel that the availability of such fast synthesis will change the way people design, creating a “new platform”. I’m not sure I see that, but perhaps they are smarter than me.

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OK, so that’s my first 3 thoughts regarding Oasys design. I’ll be getting a better look at them at DAC and will share what I learn in some upcoming blog posts. Please feel free to share your thoughts here as well. Between us, we can hopefully decide if this Oasys is real or a mirage.

harry the ASIC guy

What Makes DAC 2009 different from other DACs?

Sunday, July 12th, 2009

By Narendra (Nari) Shenoy, Technical Program Co-Chair, 46th DAC

Each year, around this time, the electronic design industry and academia meticulously prepare to showcase the latest research and technologies at the Design Automation Conference. For the casual attendee, after a few years the difference between the conferences of years past begins to dim. If you are one of them, allow me to dispel this notion and invite you to look at what is different this year.

For starters, we will be in the beautiful city of San Francisco from July 26-31. The DAC 2009 program, as in previous years, has been thoughtfully composed from using two approaches. The bottom up approach selects technical papers from a pool of submissions using a rigorous review process. This ensures that only the best technical submissions are accepted. For 2009, we see an increasing focus on research towards system level design, low power design and analysis, and physical design and manufacturability. This year, a special emphasis for the design community has been added to the program, with a User Track that runs throughout the conference. The new track, which focuses on the use of EDA tools, attracted 117 submissions reviewed by a committee made up of experienced tool users from the industry. The User Track features front end and back end sessions and a poster session that allows a perfect opportunity to interact with presenters and other DAC attendees. In addition to the traditional EDA professionals, we invite all practitioners in the design community – design tool users, hardware and software designers, application engineers, consultants, and flow/methodology developers, to come join us.

This first approach is complemented by a careful top-down selection of themes and topics in the form of panels, special sessions, keynote sessions, and management day events. The popular CEO panel returns to DAC this year as a keynote panel. The captains of the EDA industry, Aart deGeus (Synopsys), Lip-Bu Tan (Cadence) and Walden Rhines (Mentor) will explore what the future holds for EDA. The keynote on Tuesday by Fu-Chieh Hsu (TSMC), will discuss alignment of business and technology models to overcome design complexity. William Dally (Nvidia and Stanford) will present the challenges and opportunities that throughput computing provides to the EDA world in his keynote on Wednesday. Eight panels on relevant areas are spread across the conference. One panel explores whether the emphasis on Design for Manufacturing is a differentiator or a distraction. Other panels focus on a variety of themes such as confronting hardware-dependent software design, analog and mixed signal verification challenges, and various system prototyping approaches. The financial viability of Moore’s law is explored in a panel, while another panel explores the role of statistical analysis in several fields, including EDA. Lastly, we have a panel exploring the implications of recent changes in the EDA industry from an engineer’s perspective.

Special technical sessions will deal with a wide variety of themes such as preparing for design at 22nm, designing circuits in the face of uncertainty, verification of large systems on chip, bug-tracking in complex designs, novel computation models and multi-core computing. Leading researchers and industry experts will present their views on each of these topics.

Management day includes topics that tackle challenges and decision making in a complex technology and business environment. The current “green” trend is reflected in a slate of events during the afternoon of Thursday July 30th. We start with a special plenary that explores green technology and its impact on system design, public policy and our industry. A special panel investigates the system level power design challenge and finally a special session considers technologies for data centers.

Rather than considering it a hindrance to attendance, the prolonged economic malaise this year should provide a fundamental reason to participate at DAC. As a participant in the technical program, DAC offers an opportunity to share your research and win peer acclaim. As an exhibitor, it is an ideal environment to demonstrate your technology and advance your business agenda. As an attendee, you cannot afford to miss the event where “electronic design meets”. DAC provides an unparalleled chance to network and learn about advances in electronic design for everyone. Won’t you join us at the Moscone Center at the end of the month?

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This year’s DAC will be held July 26-31 at the Moscone Center in San Francisco. Register today at www.dac.com. Note also that there are 600 free DAC passes being offered courtesy of the DAC Fan Club (Atrenta, Denali, Springsoft) for those who have no other means to attend.

Why I’m a Blogger and Not an EDA Idol

Tuesday, July 7th, 2009

(WARNING: What you are about to hear is very disturbing. You may want to remove any children, pets, or small farm animals before listening to the audio in this blog post. You’ve been warned.)

Several years ago, I was driving home from a family vacation when I accidentally speed dialed my boss on the cell phone. His voice mail picked up just as I was singing in the car to my daughter. I had no idea what had occurred until a month later at a staff meeting when he got up in from of my team and my colleagues and played this audio track.

Now you know why I am not trying to become the next EDA Idol at this year’s Design Automation Conference!

Top BloggerFortunately, there is another tongue-in-cheek contest that I am honored to be part of, EDA’s Next Top Blogger.

In case you can’t make DAC this year, I’d like to introduce you to the fellow nominees because they are all great writers and experts in their domains. I encourage you to read these blogs and subscribe to the ones that you find valuable. And look beyond this list because there are many more out there.

Colin Warwick is a Product Marketing Manager at Agilent EEsof EDA group. Colin’s Signal Integrity blog is about signal integrity tips, tricks, and tutorial for multigigabit/s chip-to-chip data links. It includes videos (technical and humorous), tutorial articles, interactive calculators and polls, reviews, and product and event information.

John Busco is a Design Implementation Manager at NVidia. Blogging since 2005, John’s Semi-Blog shares high quality news and opinion about semiconductors and EDA. John is hands-on working in the trenches on the bleeding edge designs, so you can trust what he tells you.

Paul McLellan  has been an executive in EDA and Semiconductors with companies like VLSI Technologies, Compass, Ambit, Cadence,and on and on. His EDA Graffiti blog covers EDA and semiconductor, looking back to some history, analyzing the industry and looking where things are likely to end up. I always walk away from Paul’s blog posts with something to think about.

Daniel Nenni is also an EDA industry veteran with similarly impressive credentials. Although his Silicon Valley Blog is fairly new, Daniel writes like a verteran blogger, sharing his 25+ years of experience in semiconductor design and manufacture in an entertaining manner. He manages to share some of his personal life observations as well.

Karen Bartleson is Director of Community Marketing at Synopsys. Since November 2007, she has presented news, insights, and opinions on the topic of EDA standards in her ever popular The Standards Game blog. Karen is also spearheading Synopsys’ Conversation Central at DAC where you can exchange ideas with many of these same top bloggers (and many more) about how social media is changing the media landscape.

Frank Schirrmeister is Director of Product Marketing and System-Level Solutions at Synopsys. His A View From The Top blog is dedicated to System-Level Design and Embedded Software and deals with the technology and business aspects to get us to ESL and the next abstraction level eventually!

JL Gray is a hands-on verification consultant at Verilab. In his Cool Verification blog, which set the standard for independent blogging in EDA, JL shares this thoughts on hardware verification, the EDA industry, and related topics. JL spearheaded the EDA Blogger Birds-of-a-Feather session at DAC last year and sits on the ever popular Accellera Verification IP Technical Subcommittee.

I have 2 favors to ask. First, please check out some these wonderful bloggers (and some of the others you can find on David Lin’s EDA Blog Roll) who devote their evenings and weekends writing for free (well, about half of us) to bring you valuable information you can’t get anywhere else. Then, show your support by voting for your favorite blog and telling a friend or a co-worker about all this great content out there. Please vote for whoever you want, but remember, if I lose, I might have to sing next year. And you don’t want that!

(Note: The Denali site requires you to enter a Captcha phrase and also your valid email address in order to ensure that people only vote once. The email address WILL NOT be used for any other purpose, so please do not be dissuaded from voting because of this).

harry the ASIC guy

Mentor Is Listening

Thursday, June 11th, 2009

My morning routine is pretty, well, routine.

Get up.  Wake the kids.

Check email.  Ask the kids to stop jumping on the couch.

Check Twitter. Tell the kids again to stop jumping on the couch.

Check my Google Reader. Glare at the kids with that “I’ve asked you for the last time” look.

You get the idea.

This Wednesday morning, somewhere in between conversations with my kids, walking the dog, and getting ready for work, I came across the following comment on a friend’s blog:

Ron, we are listening.

http://www.mentor.com/blogs

Ron Fuller
Web Manager, Mentor Graphics

For background, Ron Ploof is the guy who got the crazy idea almost 3 years ago that Synopsys should be doing something in this new world called social media. (Actually, I don’t think the term “social media” had even been coined back then). He evangelized this belief to the VP of Marketing at Synopsys and created for himself a job as Synopsys’ “New Media Evangelist” (actual title on his business card). He launched Synopsys’ first foray into social media, including podcasts, videos, and most prominently, blogs.

Synopsys’ success motivated Cadence to follow suit (something confided to me by Cadence’s former community manager). And it seems, according to the comment on Ron’s blog, it also motivated Mentor’s move into social media.

__________

I wanted to find out more about the Mentor blogs and I was able to set up some time to talk over lunch with Sonia Harrison at Mentor (see her sing at the Denali DAC party) . Sonia had helped me set up my previous interview with Paul Hofstadler and had extended me an invitation to attend the Mentor User2User conference (which, unfortunately, I could not attend). As it turns out, Sonia was the absolutely right person to talk to.

Even though I had only now become aware of Mentor blogs, Mentor had evidently coordinated their launch with the launch of their new website several months ago. Sonia was quite humble, but it seems that she was the driving force behind the blogs and Mentor’s presence in other social media like Twitter. She had been watching what was going on for some time, hesitant to jump in without a good plan, and now was the time.

According to Sonia, Mentor’s motivation for doing the blogs was to extend into a new media their “thought leadership” in the industry, to draw customers in to their website, and to exchange information with customers. Interestingly, Mentor did not hire an outside social media consultant or community manager like Cadence had. Rather, the project was homegrown. Sonia recruited various technical experts and others as bloggers. She developed “common sense” social media guidelines to make sure bloggers were informed of and played by social media rules (e.g. no sensitive or proprietary information, be polite, respect copyrights, give attribution).

According to Sonia, “one of the more difficult things was to get people to commit to blogging regularly. Writing takes time, it’s almost a full time job.” Despite this additional work burden, Mentor has no plans to bring in professional journalists as bloggers like Richard Goering at Cadence. And it doesn’t seem they need to. Simon Favre received a blog of the week award from System Level Design a few weeks ago, so they are doing quite well on their own.

Sonia does not have any specific measurable goals (page views, subscribers, etc.), which I think is a mistake, especially when her upper management comes asking for evidence that these efforts are paying off. My friend Ron likes to tell me that social media is the most measurable media ever and it’s a shame not to use the data.

I started playing with the site later in the afternoon and noticed a few things. First, when I added a comment to one of the blogs without registering, it did not show up right away, nor did I get a message that the comment was being moderated. It did show up later in the day, but it would be nice to at least be told that it was “awaiting moderation”. Still better, why moderate or require registration at all? The likelihood of getting inappropriate comments from engineering professionals is very low, and they can always be removed if need be. Moderation of comments will also kill a hot topic in its tracks. I’ve personally had the experience of publishing a new blog post late at night and waking up to several comments, some addressing other comments. Had I moderated the blog, none of those comments would have even showed up until later in the day.

Second, there was no way to enter a URL or blog address when leaving a comment. It is pretty standard practice to have this feature to allow readers to “check out” the person leaving the comment. Hopefully thay can add this.

On the positive side, the most important feature of a blog is the content and the content looks very good, especially the PCB blogs. Also, there is apparently no internal review or censorship of blog posts, so bloggers have the freedom to write whatever they want, within the social media guidelines of course.

 __________

It’s been almost 3 years since Ron made his first pitch to his manager. Who would have thought that the Big 3 and many others would have adopted social media in such a short time. Meanwhile, my kids are still jumping on the couch.

GTG

harry the ASIC guy

Thoughts On Synopsys’ Q2 2009 Earnings Call

Thursday, May 21st, 2009

Last night you may have watched the NBA Playoff game in which the Orlando Magic came back to defeat the heavily favored Cleveland Cavaliers. Great game!!!

Or the finale of American Idol in which Kris Allen came back to defeat the heavily favored Adam Lambert. Great show!!!

What did I do last night? I listened to the Q2 2009 Synopsys earnings call. Great conference call!!!

(OK … I’ll admit it wasn’t as exciting and nail biting as either of the other viewing options. Just think of it like this: I took on the work of listening to the call and summarizing it for you, in order to free you up to watch the game or idol. You can thank me later :-) )

Here’s the summary. (You can read the full transcript here if you like).

Financials

On the up side, Synopsys had a good Q2, beating their revenue and earnings per share guidance slightly. On the down side, Synopsys lowered its revenue and cash flow guidance slightly for the rest of the year, allowing for potential customer bankruptcies, late payments, and reduced bookings. Customers are approaching Synopsys to “help them right now through this downturn”, i.e. to reduce their cost of software. It looks like the recession is finally catching up to them.

As I finish off this post on Thursday morning, it looks like the analysts agree. Synopsys shares are down 10%, so it seems they are getting punished for revising their forecast. 

Still, Synopsys is in very good financial health, with $877M in cash and short term investments. Their cash flow is going to go down the rest of the year, so they will eat into this fund, but they will still have plenty to selectively acquire strong technology that might add to their portfolio, as they did with the MIPs Analog Business Group.

Themes

There were 2 themes or phrases that kept recurring in the call that I am sure were points of emphasis for Aart.

First, the word “momentum” was used 6 times (by my count) during the call. Technology momentum. Customer momentum. Momentum in the company. Clearly, Synopsys is trying to portray an image of the company building up steam while the rest of the industry wallows in the recession.

Second, customers are “de-risking their supplier relationships”, i.e. looking to consolidate with an EDA vendor with strong financials who’ll still be there when the recession ends. Again, Synopsys is trying to portray itself as the safe choice for customers, hoping to woo customers away from less financially secure competitors like Cadence and Magma. This ties in with the flurry of “primary EDA vendor” relationships that Synopsys has announced recently.

The opportunity for Synopsys (and danger for the competition) is to pick up market share during this downturn and it looks like that may be happening as companies “de-risk” by going with the company with the “momentum” and a “extraordinarily strong position”. Or at least that’s the message that Synopsys is sending.

Technology

Aart did rattle off the usual laundry list of technology that he wanted to highlight, including some introduced last year (e.g. Z-route). Of note were the following:

  • Multi-core technology in VCS with 2x speedup (is 2x a lot?)
  • Custom Designer, which Aart called “a viable alternative to the incumbent” (ya know marketing didn’t pick the word “viable”)
  • Analog IP via the MIPS Analog Business Group acquisition, especially highlighting how that complements the Custom Designer product (do I see “design kits” in the future?)
  • The Lynx Design System (see my 5-part series)
  • IC-Validator (smells like DRC fixing in IC Compiler - Webinar today, I’ll find out more)

__________

In summary, Synopsys had a good quarter, but they have finally acknowledged that they are not immune to the downturn and they expect to get impacted the next few quarters.

harry the ASIC guy

Synopsys’ Digital to Analog Conversion

Tuesday, May 12th, 2009

Last Thursday, the same day that Synopsys announced it’s acquisition of MIPS’ Analog Business Group (ABG) for $22M in cash, I had a long overdue lunch with a former colleague of mine at Synopsys. We spent most of the time talking about family, and how each other’s jobs were going, and the economy, and the industry in general.

At some point, the discussion got around to Aart DeGeus and his leadership qualities. My friend, who plays bass guitar with Aart on occasion, shared with me his observations of Synopsys’ CEO outside of work. “He’s a born leader, even when he’s playing music,” my friend said as he related one story of how Aart lead the band in an improvisational session with the same infectious enthusiasm he brings to Synopsys. Here’s a look.

While driving back from lunch, I recalled a field conference from the mid 1990s where Aart introduced the notion of “Synopsys 2″. Synopsys 2 was to be a new company (figuratively, not literally) that would obsolete Synopsys 1 and take a new leadership role in a transforming industry. At that time, Synopsys 1 was the original “synthesis company” along with some test and simulation tools. The industry challenge driving Synopsys 2 was the need for increased designer productivity to keep up with chip sizes increasing due to the inexorable and ubiquitous Moore’s Law.

Aart’s vision for this new EDA order was twofold. First, behavioral synthesis would allow designers to design at a higher, more efficient, and more productive level of abstraction, thereby increasing their productivity. In fact, your’s truly helped develop and deliver the very first DAC floor demo of Behavioral Compiler. I also developed a very simple but elegant presentation of the power of behavioral synthesis that was used throughout Synopsys, garnered the praise of Aart himself, and sits in my desk as a memento of my time at Synopsys. Unfortunately, behavioral synthesis never really caught on at the time. Oh well. So much for that.

The second part of Aart’s productivity vision was design reuse. Needless to say, that vision has come true in spades. I don’t have reliable numbers at my finger tips, but I would guess that there is hardly a chip designed without some sort of implementation or verification IP reuse. Some chips are almost entirely reusable IP, with the only custom logic stitching it all together. I can’t imagine designing 100M gate chips without design reuse.

Design teams looking for digital IP were faced with a straightforward make vs. buy decision. On the one hand, most design teams could design the IP themselves given enough time and money. They could even prototype and verify the IP via FPGA protoytype to make sure it would work. But could they do it faster and cheaper than buying the IP and could they do it with a higher level of quality? The design team that decided they could do a better, faster, cheaper job themselves, did so. The others bought the IP.

But analog and mixed signal IP is very different. Whereas most design teams have the skills and ability to design digital IP, they usually do not have the expertise to design complex analog and mixed signal IP. Not only are analog designers more scarce, but the problem keeps getting harder at smaller geometries. Ask any analog designer you know how hard it is to design a PLL at 65 nm or 45 nm. What were 4 corner simulations at 90nm become 16 corner or even monte-carlo simulations at 45 nm and below. Not only is analog design difficult, but it often requires access to foundry specific information only available to close partners of the foundries. And even if you can get the info and design the IP, there is no quick FPGA prototype to prove it out. You need to fab a test chip (which is several months), complete with digital noise sources to stress the IP in its eventual environs. The test chip can cost several million dollars (much more than an FPGA protoype for digital IP) and you’d better count on at least one respin to get it right.

That is why Synopsys’ acquisition of the MIPS ABG IP is such a good move. The “value proposition” for analog IP is so much greater than for digital IP. It’s not a matter of whether the customer can design the IP faster, better, cheaper, it’s whether he can design it at all. By expanding its analog IP portfolio, at a bargain price, Synopsys is well positioned to provide much of the analog and mixed signal IP at 65 nm and below. In addition, this acquisition gives Synopsys a real analog design team with which they can perform design services, something they have coveted but lacked for some time.

Once again, it looks like Aart is taking the leadership role. Look for other companies to follow the leader.

harry the ASIC guy

TSMC Challenges Lynx With Flow Of Their Own

Wednesday, May 6th, 2009

About a month and a half ago, I wrote a 5 part series of blog posts on the newly introduced Lynx Design System from Synopsys:

One key feature, the inclusion of pre-qualified technology and node specific libraries in the flow, was something I had pushed for when I was previously involved with Lynx (then called Pilot). These libraries would have made Lynx into a complete out-of-the-box foundry and node specific design kit … no technology specific worries. Indeed, everyone thought that it was a good idea and would have happened had it not been for resistance from the foundries that were approached. Alas!

In the months before the announcement of Lynx, I heard that Synopsys had finally cracked that nut and that foundry libraries would be part of Lynx after all. Whilst speaking to Synopsys about Lynx in preparation for my posts, I asked whether this was the case. Given my expectations, I was rather surprised when I was told that no foundry libraries would be included as part of Lynx or as an option.

The explanation was that it proved too difficult to handle the many options that customers used. High Vt and low Vt. Regular and low power process. IO and RAM libraries from multiple vendors like ARM and Virage. Indeed, this was a very reasonable explanation to me since my experience was that all chips used some special libraries along the way. How could one QA a set of libraries for all the combinations? So, I left it at that. Besides, Synopsys offered a script that would build the Lynx node from the DesignWare TSMC Foundry Libraries.

Two weeks ago, at the TSMC Technology Symposium in San Jose, TSMC announced their own Integrated Sign-off Flow that competes with the Lynx flow, this one including their libraries. Now it seems to make sense. TSMC may  have backed out of providing libraries to Synopsys to use with Lynx since they were cooking up a flow offering of their own. I don’t know this to be a fact, but I think it’s a reasonable explanation.

So, besides the libraries, how does the TSMC flow compare to the Synopsys Lynx flow? I’m glad you asked. Here are the salient details of the TSMC offering:

  • Complete RTL to GDSII flow much like Lynx
  • Node and process specific optimizations
  • Uses multiple EDA vendors’ tools  (Synopsys mostly, but also Cadence, Mentor, and Azuro)
  • Available only for TSMC 65nm process node (at this time)
  • No cost (at least to early adopters … the press release is unclear whether TSMC will charge in the future)
  • And of course, libraries are included.

In comparison to Synopsys’ Lynx Design System, there were some notable features missing from the announcement:

  • No mention of anything like a Management Cockpit or Runtime Manager
  • No mention of how this was going to be supported
  • No mention of any chips or customers that have been through the flow

To be fair, just because these were not mentioned, does not mean that they are really missing, I have not seen a demo of the flow or spoken to TSMC (you know how to reach me) and that would help a lot in evaluating how this compares to Lynx. Still, from what I know, I’d like to give you my initial assessment of the strength of these offerings.

TSMC Integrated Signoff Flow

  • The flow includes EDA tools from multiple vendors. There is an assumption that TSMC has created a best-of-breed flow by picking the tool that performed each step in the flow the best and making all the tools work together. Synopsys will claim that their tools are all best-of-breed and that other tools can be easily integrated. But, TSMC’s flow comes that way with no additional work required. (Of course, you still need to go buy those other tools).
  • Integrated libraries, as I’ve described above. Unfortunately if you are using any 3rd party libraries, you’ll need to integrate them yourself it seems.
  • Node and process specific optimizations should provide an extra boost in quality of results.
  • Free (at least for now)

Synopsys Lynx Design System

  • You can use the flow with any foundry or technology node. A big advantage unless you are set on TSMC 65nm (which a lot of people are).
  • Other libraries and tools are easier to integrate into the flow I would think. It’s not clear whether TSMC even supports hacking the flow for other nodes.
  • Support from the Synopsys field and support center. Recall, this is now a full fledged product. Presumably, the price customers pay for Lynx will fund the support costs. If there is no cost for the TSMC flow, how will they fund supporting it? Perhaps they will take on the cost to get the silicon business, but that’s a business decision I am not privy to. And don’t underestimate the support effort. This is much like a flow that ASIC vendors (TI, Motorola/Freescale, LSI Logic), not foundries, would have offered. They had whole teams developing and QA’ing their flows. And then they would be tied to a specific set of tool releases and frozen.
  • Runtime Manager and Management Cockpit. Nice to have features.
  • Been used to create real chips before. As I’d said, the core flow in Lynx dates back almost 10 years and has been updated continuously. It’s not clear what is the genesis of the new TSMC flow. Is it a derivative of the TSMC reference flows? Is it something that has been used to create chips? Again, I don’t know, but I’ve got to give Synopsys the nod in terms of “production proven”.

So, what do I recommend. Well, if you are not going to TSMC 65 nm with TSMC standard cell libraries, then there is not much reason to look at the TSMC flow. However, if you are using the technology that TSMC currently supports, the appeal of a turnkey, optimized, and FREE flow is pretty strong. I’d at least do my due diligence and look at the TSMC flow. It might help you get better pricing from TSMC.

If anyone out there has actually seen or touched the TSMC flow, please add a comment below. Everyone would love to know what you think first hand.
harry the ASIC guy

EDA Merger Poll - What’d Be The Best Merger

Friday, May 1st, 2009

Rumors are flying concerning some big changes next week in EDA amongst the big players. It first got started by John Blyler on Twitter. Then Magma stock took off this week for no apparent reason. And rumors of a Cadence-Magma merger have been flying around for about a month since Rajeev denied them.

Something may happen or nothing may happen. But it’s always fun to speculate. So, what do you think would be the best merger of the top 4 EDA companies?

Vote here or feel free to leave your comments below. We’ll see who, if anyone, is right :-)

harry the ASIC guy