Verification Methodology Poll

In response to a recent post regarding the verification survey on the DVCon website, Jeremy Ralph of PDTi expressed that he’d “be interested to know what proportion of the SV is OVM vs. VMM”, a question that was missing from the survey. Considering the whole kerfuffle concerning OVM and VMM over the last year, I thought this would be a good question for you, the ones really using the tools. I also thought it would be a good opportunity to try out this new Doodle survey tool I was told about.

So … I created the first ASIC guy survey on Doodle. That was very easy as was casting my own vote. Now it’s your turn.


Feel free to leave a pseudonym if you wish to be anonymous. Make it funny, but keep it clean. And please don’t impersonate someone else.  I’ll know something is up if Aart votes for OVM 🙂

Also, please let other people know about this poll and ask them to vote.  The more votes we have, the more accurate the survey results. And it would be really cool if we can get more respondents online than DVCon had in person.

If this works well, I’ll continue to do this every so often. Feel free to provide suggestions for future polls.

harry the ASIC guy

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5 Responses to “Verification Methodology Poll”

  1. harry says:

    Day 1 – Feb 3, 2009

    The survey is starting to pick up steam and generate some interesting data:

    1) Early lead was for VMM, then OVM caught up, then e started to pipe up. I think there might have been some ballot stuffing going on, but I guess all’s fair.

    2) Have 30 respondents so far and only 2 (7%) are not planning to use some sort of System Verilog methodology; i.e. using Verilog or VHDL alone.

    3) 26/30 (87%) using VMM or OVM, but only 3 (10%) of those are using both (likely consultants).

    4) No AVM and only 4 using RVM/Vera. 9 (30%) using eRM/e.

    I’ll be back tomorrow with some more analysis. Feel free to post a comment with your own interpretations.


  2. Jeremy Ralph says:

    That is a pretty cool survey tool! I wonder how big the sample size needs to be for this survey to be statistically significant. Another variable that might be interesting is to know who is doing fixed (ASSP/ASIC) vs. programmable logic (FPGA) designs. My guess is that FPGA developers are more likely to use VHDL for verification.

  3. arunava says:

    What i’m wondering is why there is no “systemC” and “C/C++”?

  4. harry says:

    Regarding SystemC/C/C++, I’ve had several comments that it should have been included in the poll. Most people have been putting it in “Other”, but it probably deserves its own category.

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