Archive for October, 2010

EDA: The Next Big Things

Sunday, October 10th, 2010

As most of you know, I’ve been a big advocate for using technology to do more and more online. As an example, back in April, when the volcano in Iceland was causing havoc with air travel in Europe, I wrote a post on the Xuropa blog entitled “What’s in Your Volcano Kit?” In that post, I urged EDA companies to develop a kit of online tools to communicate and collaborate with current and prospective customers and the industry in general.

Well, it’s good to know that people are reading my blog and following my advice! 😉

One such tool that has become very popular in the last year, virtual conferences, are events sponsored either by media companies or the EDA companies themselves with several sessions throughout the day on a variety of topics. For us designers, they allow us to “drop in” on an event without leaving our desks or investing additional time or cost in traveling to and from the event. Certainly, it is not as rich an experience as being there live, but it’s more complete than the standard single topic disguised product pitch Webinar.

Since my advocacy was so fundamental in bringing these events about, I am very excited to be taking part in one of these upcoming virtual conferences. I will be moderating a session entitled “System-on-Chip: Designing Faster and Faster” at the upcoming “EDA Virtual Conference- EDA: The Next Big Things” on October 14. Here is a brief overview of my session, which will include presentations by Synopsys, Sonics, and Magma.

High speed digital design presents three important challenges: creating functional IP that performs well, combining IP blocks quickly to form a system, and being sure the system performs as expected with no surprises. EDA is allowing designers to create, simulate, connect, and deliver SoCs in new and exciting ways by combining and verifying IP blocks faster than ever. Very fast digital IP, with as high as 2 GHz clock speeds, is uncovering new issues that EDA and IP teams are working together to solve.

This session looks at the trends in digital IP, interconnect technology, issues in maintaining signal integrity, on-chip instrumentation, and more ideas to create sophisticated SoC designs and get chips to market quickly. Experts will discuss what they are seeing as clock speeds increase, tools capable of identifying issues, and ways to make sure a high speed SoC functions right the first time.

There are also 4 other 1-hour sessions during the day:

You can register for the event here. I hope you can make it.

harry the ASIC guy