Archive for February, 2011

How One Designer Started His Company – Agnisys

Monday, February 28th, 2011


I met Anupam Bakshia last year as one of the winner’s of the Xuropa Do More With Less Contest. We’ve kept in touch since then, so when he mentioned that he was going to be a first time exhibitor at DVCon, I was thrilled. Bootstrapping a company is difficult, and attending a conference is a big commitment of time and resources. Anupam asked for Xuropa‘s help, so if you go to DVCon this week you will see me in the Agnisys booth. Please stop by and say hello to me and, more importantly, to Anupam.

I also thought it would be interesting to understand how and why Anupam started Agnisys. He was gracious enough to take some time to answer my questions.

Harry: Tell me a little bit about your background?

Anupam: I started my career at Gateway Design Automation (the company that created Verilog), which was later acquired by Cadence Design System where I was responsible for creating Verilog simulation libraries for various foundries. From the very beginning, I despised manual, error prone, laborious work and was often the first in the company to create new Perl based utilities to automate as much as possible. I then joined PictureTel and later Avid where I continued my pursuit of Automation-Nirvana – a design and verification process where no time is wasted, where there is a single source, no duplication ….

Harry: Was there a problem that you encountered that led you to create the products you developed at Agnisys?

Anupam: Yes, my experience at high tech companies helped me understand the typical design and verification challenges the development team face. Both at AVID and PictureTel I was lucky to have bosses that allowed me a free reign to spend a lot of time working with engineers to create useful utilities. It was very gratifying to see happy people using the tools that I created.

Harry: Why and how did you go from working in CAE/Verification groups to starting your own company?

Anupam: These companies were great, but there was a limit to how much time and resources I could spend on tangential activities like creating tools and scripts for process improvement. So I launched this company to work on such process improvement utilities full time and with a dedicated team of people.

Harry: Last year, Agnisys was one of the winners of the Xuropa Do More With Less Contest. Tell us how Agnisys as a company is doing more with less and how your tools help your customers do more with less.

Anupam: We fundamentally believe in doing more with less. We enable our customers to do the same.

Harry: So, IDesignSpec was your company’s first product. Tell me more about what it does?

Anupam: IDesignSpec(IDS) was our first product and it won an award the same year it was launched. It can basically take a register specification and create all the downstream code and documentation from it. Over the years we have added more and more capability and now it is kind of universal register transformation tool. So it can create almost anything from any form of input data.

Harry: Has the importance of this type of tool increased with release of UVM?

Anupam: Yes absolutely! UVM now has a register package however, it doesn’t come with a register generator. IDS fills the void, because it can take your IP-XACT, SystemRDL, Word, Excel, OpenOffice register documentation and create UVM code from it.

Harry: What about IVerifySpec, and IAssertSpec?

Anupam: While IDesignSpec solves a niche problem of managing register data, IVerifySpec solves a broader problem of verification. It enables users to create vendor-neutral plans for verification, monitor their execution and manage gobs and gobs of data associated with modern day verification of large ASICs and FPGAs.
IAssertSpec is a new tool that we have developed, it is basically a “decoder ring” for SVA!

Harry: In closing, do you have anything special planned for DVCon this year?

Anupam: Absolutely! This is our first DVCon and we are very excited to meet all the engineers and show all the exciting things we have for them. Specifically, we are giving away a plug-in for Microsoft Excel capable of generating UVM. We also have a short Quiz for SystemVerilog Assertions that people can test their skills, and if you score in the top 25%, you get a gift!!