Posts Tagged ‘SoC’

Hot Topics from SNUG San Jose 2008 – Day 1 AM

Monday, March 31st, 2008

I just attended Aart DeGeus’ keynote address at SNUG 2008 and there were two highlights:

  1. Synopsys is back in the analog design market! Filling the gap in their product portfolio, they announced a new in-house developed product called Orion that is aiming directly at the Cadence users of Virtuoso. Orion is in beta right now and will work with Open Access. They did a canned demo and highlighted ease-of-use and productivity over Virtuoso.
  2. Besides questions on Orion, all the other questions were regarding VMM / OVM and the path to getting a truly open standard verification methodology. Cliff Cummings and John Cooley asked the most direct questions on this topic, such as:
  • Will VMM ever be truly open and not just licensed?
  • Is there any attempt to speak directly to Mentor and Cadence to try to combine OVM and VMM?
  • Can we use VMM with another System Verilog simulator?

Synopsys’ plan is to donate VMM to Accellera and have Accellera drive a standard verification methodology. When asked about working with Mentor/Cadence, Synopsys asked the designers to try to push them to the table within Accellera. I expect this battle will continue.

More later…. harry the ASIC guy